Line data Source code
1 : /* SPDX-License-Identifier: BSD-3-Clause
2 : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.
4 : * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : */
6 :
7 : #include "spdk/stdinc.h"
8 :
9 : #include "nvme_internal.h"
10 : #include "nvme_io_msg.h"
11 :
12 : #include "spdk/env.h"
13 : #include "spdk/string.h"
14 : #include "spdk/endian.h"
15 :
16 : struct nvme_active_ns_ctx;
17 :
18 : static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
19 : struct nvme_async_event_request *aer);
20 : static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
21 : static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
22 : static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
23 : static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
24 : static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr);
25 : static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
26 : uint64_t timeout_in_ms);
27 :
28 : static int
29 477891 : nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2)
30 : {
31 477891 : if (ns1->id < ns2->id) {
32 164867 : return -1;
33 313024 : } else if (ns1->id > ns2->id) {
34 276062 : return 1;
35 : } else {
36 36962 : return 0;
37 : }
38 : }
39 :
40 599404 : RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp);
41 :
42 : #define CTRLR_STRING(ctrlr) \
43 : ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \
44 : ctrlr->trid.subnqn : ctrlr->trid.traddr)
45 :
46 : #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \
47 : SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
48 :
49 : #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \
50 : SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
51 :
52 : #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \
53 : SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
54 :
55 : #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \
56 : SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
57 :
58 : #ifdef DEBUG
59 : #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \
60 : SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
61 : #else
62 : #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0)
63 : #endif
64 :
65 : #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \
66 : nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
67 : offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
68 :
69 : #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \
70 : nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \
71 : offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg)
72 :
73 : #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \
74 : nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg)
75 :
76 : #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \
77 : nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg)
78 :
79 : #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
80 : nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
81 :
82 : #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
83 : nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
84 :
85 : #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \
86 : nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg)
87 :
88 : static int
89 0 : nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
90 : {
91 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
92 : &cc->raw);
93 : }
94 :
95 : static int
96 0 : nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
97 : {
98 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
99 : &csts->raw);
100 : }
101 :
102 : int
103 0 : nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
104 : {
105 0 : return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
106 : &cap->raw);
107 : }
108 :
109 : int
110 1 : nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
111 : {
112 1 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
113 : &vs->raw);
114 : }
115 :
116 : int
117 0 : nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
118 : {
119 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
120 : &cmbsz->raw);
121 : }
122 :
123 : int
124 0 : nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
125 : {
126 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
127 : &pmrcap->raw);
128 : }
129 :
130 : int
131 0 : nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo)
132 : {
133 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw),
134 : &bpinfo->raw);
135 : }
136 :
137 : int
138 0 : nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel)
139 : {
140 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw),
141 : bprsel->raw);
142 : }
143 :
144 : int
145 0 : nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value)
146 : {
147 0 : return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl),
148 : bpmbl_value);
149 : }
150 :
151 : static int
152 0 : nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
153 : {
154 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
155 : nssr_value);
156 : }
157 :
158 : bool
159 33 : nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
160 : {
161 35 : return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
162 2 : ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
163 : }
164 :
165 : /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
166 : * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
167 : */
168 : void
169 2 : spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
170 : {
171 2 : char host_id_str[SPDK_UUID_STRING_LEN];
172 :
173 2 : assert(opts);
174 :
175 2 : opts->opts_size = opts_size;
176 :
177 : #define FIELD_OK(field) \
178 : offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
179 :
180 : #define SET_FIELD(field, value) \
181 : if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
182 : opts->field = value; \
183 : } \
184 :
185 2 : SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
186 2 : SET_FIELD(use_cmb_sqs, false);
187 2 : SET_FIELD(no_shn_notification, false);
188 2 : SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
189 2 : SET_FIELD(arbitration_burst, 0);
190 2 : SET_FIELD(low_priority_weight, 0);
191 2 : SET_FIELD(medium_priority_weight, 0);
192 2 : SET_FIELD(high_priority_weight, 0);
193 2 : SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
194 2 : SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
195 2 : SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
196 :
197 2 : if (nvme_driver_init() == 0) {
198 2 : if (FIELD_OK(hostnqn)) {
199 1 : spdk_uuid_fmt_lower(host_id_str, sizeof(host_id_str),
200 1 : &g_spdk_nvme_driver->default_extended_host_id);
201 1 : snprintf(opts->hostnqn, sizeof(opts->hostnqn),
202 : "nqn.2014-08.org.nvmexpress:uuid:%s", host_id_str);
203 : }
204 :
205 2 : if (FIELD_OK(extended_host_id)) {
206 1 : memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
207 : sizeof(opts->extended_host_id));
208 : }
209 :
210 : }
211 :
212 2 : SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
213 :
214 2 : if (FIELD_OK(src_addr)) {
215 1 : memset(opts->src_addr, 0, sizeof(opts->src_addr));
216 : }
217 :
218 2 : if (FIELD_OK(src_svcid)) {
219 1 : memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
220 : }
221 :
222 2 : if (FIELD_OK(host_id)) {
223 1 : memset(opts->host_id, 0, sizeof(opts->host_id));
224 : }
225 :
226 2 : SET_FIELD(command_set, CHAR_BIT);
227 2 : SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
228 2 : SET_FIELD(header_digest, false);
229 2 : SET_FIELD(data_digest, false);
230 2 : SET_FIELD(disable_error_logging, false);
231 2 : SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
232 2 : SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
233 2 : SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
234 2 : SET_FIELD(disable_read_ana_log_page, false);
235 2 : SET_FIELD(disable_read_changed_ns_list_log_page, false);
236 :
237 2 : if (FIELD_OK(psk)) {
238 1 : memset(opts->psk, 0, sizeof(opts->psk));
239 : }
240 :
241 : #undef FIELD_OK
242 : #undef SET_FIELD
243 2 : }
244 :
245 : const struct spdk_nvme_ctrlr_opts *
246 0 : spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr)
247 : {
248 0 : return &ctrlr->opts;
249 : }
250 :
251 : /**
252 : * This function will be called when the process allocates the IO qpair.
253 : * Note: the ctrlr_lock must be held when calling this function.
254 : */
255 : static void
256 15 : nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
257 : {
258 : struct spdk_nvme_ctrlr_process *active_proc;
259 15 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
260 :
261 15 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
262 15 : if (active_proc) {
263 0 : TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
264 0 : qpair->active_proc = active_proc;
265 : }
266 15 : }
267 :
268 : /**
269 : * This function will be called when the process frees the IO qpair.
270 : * Note: the ctrlr_lock must be held when calling this function.
271 : */
272 : static void
273 15 : nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
274 : {
275 : struct spdk_nvme_ctrlr_process *active_proc;
276 15 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
277 : struct spdk_nvme_qpair *active_qpair, *tmp_qpair;
278 :
279 15 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
280 15 : if (!active_proc) {
281 15 : return;
282 : }
283 :
284 0 : TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
285 : per_process_tailq, tmp_qpair) {
286 0 : if (active_qpair == qpair) {
287 0 : TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
288 : active_qpair, per_process_tailq);
289 :
290 0 : break;
291 : }
292 : }
293 : }
294 :
295 : void
296 27 : spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
297 : struct spdk_nvme_io_qpair_opts *opts,
298 : size_t opts_size)
299 : {
300 27 : assert(ctrlr);
301 :
302 27 : assert(opts);
303 :
304 27 : memset(opts, 0, opts_size);
305 :
306 : #define FIELD_OK(field) \
307 : offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
308 :
309 27 : if (FIELD_OK(qprio)) {
310 27 : opts->qprio = SPDK_NVME_QPRIO_URGENT;
311 : }
312 :
313 27 : if (FIELD_OK(io_queue_size)) {
314 27 : opts->io_queue_size = ctrlr->opts.io_queue_size;
315 : }
316 :
317 27 : if (FIELD_OK(io_queue_requests)) {
318 26 : opts->io_queue_requests = ctrlr->opts.io_queue_requests;
319 : }
320 :
321 27 : if (FIELD_OK(delay_cmd_submit)) {
322 26 : opts->delay_cmd_submit = false;
323 : }
324 :
325 27 : if (FIELD_OK(sq.vaddr)) {
326 26 : opts->sq.vaddr = NULL;
327 : }
328 :
329 27 : if (FIELD_OK(sq.paddr)) {
330 26 : opts->sq.paddr = 0;
331 : }
332 :
333 27 : if (FIELD_OK(sq.buffer_size)) {
334 26 : opts->sq.buffer_size = 0;
335 : }
336 :
337 27 : if (FIELD_OK(cq.vaddr)) {
338 26 : opts->cq.vaddr = NULL;
339 : }
340 :
341 27 : if (FIELD_OK(cq.paddr)) {
342 26 : opts->cq.paddr = 0;
343 : }
344 :
345 27 : if (FIELD_OK(cq.buffer_size)) {
346 26 : opts->cq.buffer_size = 0;
347 : }
348 :
349 27 : if (FIELD_OK(create_only)) {
350 26 : opts->create_only = false;
351 : }
352 :
353 27 : if (FIELD_OK(async_mode)) {
354 26 : opts->async_mode = false;
355 : }
356 :
357 : #undef FIELD_OK
358 27 : }
359 :
360 : static struct spdk_nvme_qpair *
361 22 : nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
362 : const struct spdk_nvme_io_qpair_opts *opts)
363 : {
364 : int32_t qid;
365 : struct spdk_nvme_qpair *qpair;
366 : union spdk_nvme_cc_register cc;
367 :
368 22 : if (!ctrlr) {
369 0 : return NULL;
370 : }
371 :
372 22 : nvme_ctrlr_lock(ctrlr);
373 22 : cc.raw = ctrlr->process_init_cc.raw;
374 :
375 22 : if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
376 2 : nvme_ctrlr_unlock(ctrlr);
377 2 : return NULL;
378 : }
379 :
380 : /*
381 : * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
382 : * default round robin arbitration method.
383 : */
384 20 : if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
385 3 : NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n");
386 3 : nvme_ctrlr_unlock(ctrlr);
387 3 : return NULL;
388 : }
389 :
390 17 : qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
391 17 : if (qid < 0) {
392 2 : nvme_ctrlr_unlock(ctrlr);
393 2 : return NULL;
394 : }
395 :
396 15 : qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
397 15 : if (qpair == NULL) {
398 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n");
399 0 : spdk_nvme_ctrlr_free_qid(ctrlr, qid);
400 0 : nvme_ctrlr_unlock(ctrlr);
401 0 : return NULL;
402 : }
403 :
404 15 : TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
405 :
406 15 : nvme_ctrlr_proc_add_io_qpair(qpair);
407 :
408 15 : nvme_ctrlr_unlock(ctrlr);
409 :
410 15 : return qpair;
411 : }
412 :
413 : int
414 15 : spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
415 : {
416 : int rc;
417 :
418 15 : if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
419 0 : return -EISCONN;
420 : }
421 :
422 15 : nvme_ctrlr_lock(ctrlr);
423 15 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
424 15 : nvme_ctrlr_unlock(ctrlr);
425 :
426 15 : if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
427 0 : spdk_delay_us(100);
428 : }
429 :
430 15 : return rc;
431 : }
432 :
433 : void
434 0 : spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
435 : {
436 0 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
437 :
438 0 : nvme_ctrlr_lock(ctrlr);
439 0 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
440 0 : nvme_ctrlr_unlock(ctrlr);
441 0 : }
442 :
443 : struct spdk_nvme_qpair *
444 23 : spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
445 : const struct spdk_nvme_io_qpair_opts *user_opts,
446 : size_t opts_size)
447 : {
448 :
449 23 : struct spdk_nvme_qpair *qpair = NULL;
450 23 : struct spdk_nvme_io_qpair_opts opts;
451 : int rc;
452 :
453 23 : nvme_ctrlr_lock(ctrlr);
454 :
455 23 : if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) {
456 : /* When controller is resetting or initializing, free_io_qids is deleted or not created yet.
457 : * We can't create IO qpair in that case */
458 1 : goto unlock;
459 : }
460 :
461 : /*
462 : * Get the default options, then overwrite them with the user-provided options
463 : * up to opts_size.
464 : *
465 : * This allows for extensions of the opts structure without breaking
466 : * ABI compatibility.
467 : */
468 22 : spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
469 22 : if (user_opts) {
470 18 : memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
471 :
472 : /* If user passes buffers, make sure they're big enough for the requested queue size */
473 18 : if (opts.sq.vaddr) {
474 0 : if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
475 0 : NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n",
476 : opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
477 0 : goto unlock;
478 : }
479 : }
480 18 : if (opts.cq.vaddr) {
481 0 : if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
482 0 : NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n",
483 : opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
484 0 : goto unlock;
485 : }
486 : }
487 : }
488 :
489 22 : qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
490 :
491 22 : if (qpair == NULL || opts.create_only == true) {
492 7 : goto unlock;
493 : }
494 :
495 15 : rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
496 15 : if (rc != 0) {
497 1 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n");
498 1 : nvme_ctrlr_proc_remove_io_qpair(qpair);
499 1 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
500 1 : spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
501 1 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
502 1 : qpair = NULL;
503 1 : goto unlock;
504 : }
505 :
506 23 : unlock:
507 23 : nvme_ctrlr_unlock(ctrlr);
508 :
509 23 : return qpair;
510 : }
511 :
512 : int
513 8 : spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
514 : {
515 : struct spdk_nvme_ctrlr *ctrlr;
516 : enum nvme_qpair_state qpair_state;
517 : int rc;
518 :
519 8 : assert(qpair != NULL);
520 8 : assert(nvme_qpair_is_admin_queue(qpair) == false);
521 8 : assert(qpair->ctrlr != NULL);
522 :
523 8 : ctrlr = qpair->ctrlr;
524 8 : nvme_ctrlr_lock(ctrlr);
525 8 : qpair_state = nvme_qpair_get_state(qpair);
526 :
527 8 : if (ctrlr->is_removed) {
528 2 : rc = -ENODEV;
529 2 : goto out;
530 : }
531 :
532 6 : if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
533 2 : rc = -EAGAIN;
534 2 : goto out;
535 : }
536 :
537 4 : if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
538 2 : rc = -ENXIO;
539 2 : goto out;
540 : }
541 :
542 2 : if (qpair_state != NVME_QPAIR_DISCONNECTED) {
543 1 : rc = 0;
544 1 : goto out;
545 : }
546 :
547 1 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
548 1 : if (rc) {
549 0 : rc = -EAGAIN;
550 0 : goto out;
551 : }
552 :
553 1 : out:
554 8 : nvme_ctrlr_unlock(ctrlr);
555 8 : return rc;
556 : }
557 :
558 : spdk_nvme_qp_failure_reason
559 0 : spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
560 : {
561 0 : return ctrlr->adminq->transport_failure_reason;
562 : }
563 :
564 : /*
565 : * This internal function will attempt to take the controller
566 : * lock before calling disconnect on a controller qpair.
567 : * Functions already holding the controller lock should
568 : * call nvme_transport_ctrlr_disconnect_qpair directly.
569 : */
570 : void
571 0 : nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
572 : {
573 0 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
574 :
575 0 : assert(ctrlr != NULL);
576 0 : nvme_ctrlr_lock(ctrlr);
577 0 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
578 0 : nvme_ctrlr_unlock(ctrlr);
579 0 : }
580 :
581 : int
582 14 : spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
583 : {
584 : struct spdk_nvme_ctrlr *ctrlr;
585 :
586 14 : if (qpair == NULL) {
587 0 : return 0;
588 : }
589 :
590 14 : ctrlr = qpair->ctrlr;
591 :
592 14 : if (qpair->in_completion_context) {
593 : /*
594 : * There are many cases where it is convenient to delete an io qpair in the context
595 : * of that qpair's completion routine. To handle this properly, set a flag here
596 : * so that the completion routine will perform an actual delete after the context
597 : * unwinds.
598 : */
599 0 : qpair->delete_after_completion_context = 1;
600 0 : return 0;
601 : }
602 :
603 14 : qpair->destroy_in_progress = 1;
604 :
605 14 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
606 :
607 14 : if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) {
608 0 : spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
609 : }
610 :
611 : /* Do not retry. */
612 14 : nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
613 :
614 : /* In the multi-process case, a process may call this function on a foreign
615 : * I/O qpair (i.e. one that this process did not create) when that qpairs process
616 : * exits unexpectedly. In that case, we must not try to abort any reqs associated
617 : * with that qpair, since the callbacks will also be foreign to this process.
618 : */
619 14 : if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
620 14 : nvme_qpair_abort_all_queued_reqs(qpair);
621 : }
622 :
623 14 : nvme_ctrlr_lock(ctrlr);
624 :
625 14 : nvme_ctrlr_proc_remove_io_qpair(qpair);
626 :
627 14 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
628 14 : spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
629 :
630 14 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
631 14 : nvme_ctrlr_unlock(ctrlr);
632 14 : return 0;
633 : }
634 :
635 : static void
636 3 : nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
637 : struct spdk_nvme_intel_log_page_directory *log_page_directory)
638 : {
639 3 : if (log_page_directory == NULL) {
640 0 : return;
641 : }
642 :
643 3 : assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL);
644 :
645 3 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
646 :
647 3 : if (log_page_directory->read_latency_log_len ||
648 2 : (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
649 2 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
650 : }
651 3 : if (log_page_directory->write_latency_log_len ||
652 2 : (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
653 2 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
654 : }
655 3 : if (log_page_directory->temperature_statistics_log_len) {
656 2 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
657 : }
658 3 : if (log_page_directory->smart_log_len) {
659 1 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
660 : }
661 3 : if (log_page_directory->marketing_description_log_len) {
662 1 : ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
663 : }
664 : }
665 :
666 : struct intel_log_pages_ctx {
667 : struct spdk_nvme_intel_log_page_directory log_page_directory;
668 : struct spdk_nvme_ctrlr *ctrlr;
669 : };
670 :
671 : static void
672 1 : nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl)
673 : {
674 1 : struct intel_log_pages_ctx *ctx = arg;
675 1 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
676 :
677 1 : if (!spdk_nvme_cpl_is_error(cpl)) {
678 1 : nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory);
679 : }
680 :
681 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
682 1 : ctrlr->opts.admin_timeout_ms);
683 1 : free(ctx);
684 1 : }
685 :
686 : static int
687 1 : nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
688 : {
689 1 : int rc = 0;
690 : struct intel_log_pages_ctx *ctx;
691 :
692 1 : ctx = calloc(1, sizeof(*ctx));
693 1 : if (!ctx) {
694 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
695 0 : ctrlr->opts.admin_timeout_ms);
696 0 : return 0;
697 : }
698 :
699 1 : ctx->ctrlr = ctrlr;
700 :
701 1 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
702 1 : SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory,
703 : sizeof(struct spdk_nvme_intel_log_page_directory),
704 : 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx);
705 1 : if (rc != 0) {
706 0 : free(ctx);
707 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
708 0 : ctrlr->opts.admin_timeout_ms);
709 0 : return 0;
710 : }
711 :
712 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES,
713 1 : ctrlr->opts.admin_timeout_ms);
714 :
715 1 : return 0;
716 : }
717 :
718 : static int
719 4 : nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
720 : {
721 : uint32_t ana_log_page_size;
722 :
723 4 : ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
724 4 : sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count *
725 : sizeof(uint32_t);
726 :
727 : /* Number of active namespaces may have changed.
728 : * Check if ANA log page fits into existing buffer.
729 : */
730 4 : if (ana_log_page_size > ctrlr->ana_log_page_size) {
731 : void *new_buffer;
732 :
733 4 : if (ctrlr->ana_log_page) {
734 1 : new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size);
735 : } else {
736 3 : new_buffer = calloc(1, ana_log_page_size);
737 : }
738 :
739 4 : if (!new_buffer) {
740 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n",
741 : ana_log_page_size);
742 0 : return -ENXIO;
743 : }
744 :
745 4 : ctrlr->ana_log_page = new_buffer;
746 4 : if (ctrlr->copied_ana_desc) {
747 1 : new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size);
748 : } else {
749 3 : new_buffer = calloc(1, ana_log_page_size);
750 : }
751 :
752 4 : if (!new_buffer) {
753 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n",
754 : ana_log_page_size);
755 0 : return -ENOMEM;
756 : }
757 :
758 4 : ctrlr->copied_ana_desc = new_buffer;
759 4 : ctrlr->ana_log_page_size = ana_log_page_size;
760 : }
761 :
762 4 : return 0;
763 : }
764 :
765 : static int
766 4 : nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
767 : {
768 : struct nvme_completion_poll_status *status;
769 : int rc;
770 :
771 4 : rc = nvme_ctrlr_alloc_ana_log_page(ctrlr);
772 4 : if (rc != 0) {
773 0 : return rc;
774 : }
775 :
776 4 : status = calloc(1, sizeof(*status));
777 4 : if (status == NULL) {
778 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
779 0 : return -ENOMEM;
780 : }
781 :
782 4 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
783 4 : SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
784 : ctrlr->ana_log_page_size, 0,
785 : nvme_completion_poll_cb, status);
786 4 : if (rc != 0) {
787 0 : free(status);
788 0 : return rc;
789 : }
790 :
791 4 : if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
792 4 : ctrlr->opts.admin_timeout_ms * 1000)) {
793 0 : if (!status->timed_out) {
794 0 : free(status);
795 : }
796 0 : return -EIO;
797 : }
798 :
799 4 : free(status);
800 4 : return 0;
801 : }
802 :
803 : static int
804 5 : nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
805 : void *cb_arg)
806 : {
807 5 : struct spdk_nvme_ctrlr *ctrlr = cb_arg;
808 : struct spdk_nvme_ns *ns;
809 : uint32_t i, nsid;
810 :
811 14 : for (i = 0; i < desc->num_of_nsid; i++) {
812 9 : nsid = desc->nsid[i];
813 9 : if (nsid == 0 || nsid > ctrlr->cdata.nn) {
814 0 : continue;
815 : }
816 :
817 9 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
818 9 : assert(ns != NULL);
819 :
820 9 : ns->ana_group_id = desc->ana_group_id;
821 9 : ns->ana_state = desc->ana_state;
822 : }
823 :
824 5 : return 0;
825 : }
826 :
827 : int
828 4 : nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
829 : spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
830 : {
831 : struct spdk_nvme_ana_group_descriptor *copied_desc;
832 : uint8_t *orig_desc;
833 : uint32_t i, desc_size, copy_len;
834 4 : int rc = 0;
835 :
836 4 : if (ctrlr->ana_log_page == NULL) {
837 0 : return -EINVAL;
838 : }
839 :
840 4 : copied_desc = ctrlr->copied_ana_desc;
841 :
842 4 : orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page);
843 4 : copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page);
844 :
845 9 : for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
846 5 : memcpy(copied_desc, orig_desc, copy_len);
847 :
848 5 : rc = cb_fn(copied_desc, cb_arg);
849 5 : if (rc != 0) {
850 0 : break;
851 : }
852 :
853 5 : desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) +
854 5 : copied_desc->num_of_nsid * sizeof(uint32_t);
855 5 : orig_desc += desc_size;
856 5 : copy_len -= desc_size;
857 : }
858 :
859 4 : return rc;
860 : }
861 :
862 : static int
863 16 : nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
864 : {
865 16 : int rc = 0;
866 :
867 16 : memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
868 : /* Mandatory pages */
869 16 : ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
870 16 : ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
871 16 : ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
872 16 : if (ctrlr->cdata.lpa.celp) {
873 1 : ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
874 : }
875 :
876 16 : if (ctrlr->cdata.cmic.ana_reporting) {
877 2 : ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
878 2 : if (!ctrlr->opts.disable_read_ana_log_page) {
879 2 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
880 2 : if (rc == 0) {
881 2 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
882 : ctrlr);
883 : }
884 : }
885 : }
886 :
887 16 : if (ctrlr->cdata.ctratt.fdps) {
888 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true;
889 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true;
890 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true;
891 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true;
892 : }
893 :
894 16 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL &&
895 1 : ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE &&
896 1 : !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
897 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES,
898 1 : ctrlr->opts.admin_timeout_ms);
899 :
900 : } else {
901 15 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
902 15 : ctrlr->opts.admin_timeout_ms);
903 :
904 : }
905 :
906 16 : return rc;
907 : }
908 :
909 : static void
910 1 : nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
911 : {
912 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
913 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
914 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
915 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
916 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
917 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
918 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
919 1 : }
920 :
921 : static void
922 18 : nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
923 : {
924 : uint32_t cdw11;
925 : struct nvme_completion_poll_status *status;
926 :
927 18 : if (ctrlr->opts.arbitration_burst == 0) {
928 16 : return;
929 : }
930 :
931 2 : if (ctrlr->opts.arbitration_burst > 7) {
932 1 : NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n");
933 1 : return;
934 : }
935 :
936 1 : status = calloc(1, sizeof(*status));
937 1 : if (!status) {
938 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
939 0 : return;
940 : }
941 :
942 1 : cdw11 = ctrlr->opts.arbitration_burst;
943 :
944 1 : if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
945 1 : cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
946 1 : cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
947 1 : cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
948 : }
949 :
950 1 : if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
951 : cdw11, 0, NULL, 0,
952 : nvme_completion_poll_cb, status) < 0) {
953 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n");
954 0 : free(status);
955 0 : return;
956 : }
957 :
958 1 : if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
959 1 : ctrlr->opts.admin_timeout_ms * 1000)) {
960 0 : NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n");
961 : }
962 :
963 1 : if (!status->timed_out) {
964 1 : free(status);
965 : }
966 : }
967 :
968 : static void
969 16 : nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
970 : {
971 16 : memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
972 : /* Mandatory features */
973 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
974 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
975 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
976 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
977 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
978 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
979 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
980 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
981 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
982 : /* Optional features */
983 16 : if (ctrlr->cdata.vwc.present) {
984 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
985 : }
986 16 : if (ctrlr->cdata.apsta.supported) {
987 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
988 : }
989 16 : if (ctrlr->cdata.hmpre) {
990 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
991 : }
992 16 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
993 1 : nvme_ctrlr_set_intel_supported_features(ctrlr);
994 : }
995 :
996 16 : nvme_ctrlr_set_arbitration_feature(ctrlr);
997 16 : }
998 :
999 : bool
1000 0 : spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
1001 : {
1002 0 : return ctrlr->is_failed;
1003 : }
1004 :
1005 : void
1006 1 : nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
1007 : {
1008 : /*
1009 : * Set the flag here and leave the work failure of qpairs to
1010 : * spdk_nvme_qpair_process_completions().
1011 : */
1012 1 : if (hot_remove) {
1013 0 : ctrlr->is_removed = true;
1014 : }
1015 :
1016 1 : if (ctrlr->is_failed) {
1017 0 : NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n");
1018 0 : return;
1019 : }
1020 :
1021 1 : if (ctrlr->is_disconnecting) {
1022 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n");
1023 0 : return;
1024 : }
1025 :
1026 1 : ctrlr->is_failed = true;
1027 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1028 1 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1029 1 : NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n");
1030 : }
1031 :
1032 : /**
1033 : * This public API function will try to take the controller lock.
1034 : * Any private functions being called from a thread already holding
1035 : * the ctrlr lock should call nvme_ctrlr_fail directly.
1036 : */
1037 : void
1038 0 : spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
1039 : {
1040 0 : nvme_ctrlr_lock(ctrlr);
1041 0 : nvme_ctrlr_fail(ctrlr, false);
1042 0 : nvme_ctrlr_unlock(ctrlr);
1043 0 : }
1044 :
1045 : static void
1046 38 : nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1047 : {
1048 38 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1049 38 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1050 :
1051 38 : if (spdk_nvme_cpl_is_error(cpl)) {
1052 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1053 0 : ctx->shutdown_complete = true;
1054 0 : return;
1055 : }
1056 :
1057 38 : if (ctrlr->opts.no_shn_notification) {
1058 0 : ctx->shutdown_complete = true;
1059 0 : return;
1060 : }
1061 :
1062 : /*
1063 : * The NVMe specification defines RTD3E to be the time between
1064 : * setting SHN = 1 until the controller will set SHST = 10b.
1065 : * If the device doesn't report RTD3 entry latency, or if it
1066 : * reports RTD3 entry latency less than 10 seconds, pick
1067 : * 10 seconds as a reasonable amount of time to
1068 : * wait before proceeding.
1069 : */
1070 38 : NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
1071 38 : ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
1072 38 : ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
1073 38 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms);
1074 :
1075 38 : ctx->shutdown_start_tsc = spdk_get_ticks();
1076 38 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1077 : }
1078 :
1079 : static void
1080 38 : nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1081 : {
1082 38 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1083 38 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1084 : union spdk_nvme_cc_register cc;
1085 : int rc;
1086 :
1087 38 : if (spdk_nvme_cpl_is_error(cpl)) {
1088 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1089 0 : ctx->shutdown_complete = true;
1090 0 : return;
1091 : }
1092 :
1093 38 : assert(value <= UINT32_MAX);
1094 38 : cc.raw = (uint32_t)value;
1095 :
1096 38 : if (ctrlr->opts.no_shn_notification) {
1097 0 : NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n");
1098 0 : if (cc.bits.en == 0) {
1099 0 : ctx->shutdown_complete = true;
1100 0 : return;
1101 : }
1102 :
1103 0 : cc.bits.en = 0;
1104 : } else {
1105 38 : cc.bits.shn = SPDK_NVME_SHN_NORMAL;
1106 : }
1107 :
1108 38 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx);
1109 38 : if (rc != 0) {
1110 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1111 0 : ctx->shutdown_complete = true;
1112 : }
1113 : }
1114 :
1115 : static void
1116 46 : nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
1117 : struct nvme_ctrlr_detach_ctx *ctx)
1118 : {
1119 : int rc;
1120 :
1121 46 : if (ctrlr->is_removed) {
1122 0 : ctx->shutdown_complete = true;
1123 0 : return;
1124 : }
1125 :
1126 46 : if (ctrlr->adminq == NULL ||
1127 39 : ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) {
1128 8 : NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n");
1129 8 : ctx->shutdown_complete = true;
1130 8 : return;
1131 : }
1132 :
1133 38 : ctx->state = NVME_CTRLR_DETACH_SET_CC;
1134 38 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx);
1135 38 : if (rc != 0) {
1136 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1137 0 : ctx->shutdown_complete = true;
1138 : }
1139 : }
1140 :
1141 : static void
1142 38 : nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1143 : {
1144 38 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1145 :
1146 38 : if (spdk_nvme_cpl_is_error(cpl)) {
1147 0 : NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n");
1148 0 : ctx->shutdown_complete = true;
1149 0 : return;
1150 : }
1151 :
1152 38 : assert(value <= UINT32_MAX);
1153 38 : ctx->csts.raw = (uint32_t)value;
1154 38 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE;
1155 : }
1156 :
1157 : static int
1158 76 : nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
1159 : struct nvme_ctrlr_detach_ctx *ctx)
1160 : {
1161 : union spdk_nvme_csts_register csts;
1162 : uint32_t ms_waited;
1163 :
1164 76 : switch (ctx->state) {
1165 0 : case NVME_CTRLR_DETACH_SET_CC:
1166 : case NVME_CTRLR_DETACH_GET_CSTS:
1167 : /* We're still waiting for the register operation to complete */
1168 0 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1169 0 : return -EAGAIN;
1170 :
1171 38 : case NVME_CTRLR_DETACH_CHECK_CSTS:
1172 38 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS;
1173 38 : if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) {
1174 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
1175 0 : return -EIO;
1176 : }
1177 38 : return -EAGAIN;
1178 :
1179 38 : case NVME_CTRLR_DETACH_GET_CSTS_DONE:
1180 38 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1181 38 : break;
1182 :
1183 0 : default:
1184 0 : assert(0 && "Should never happen");
1185 : return -EINVAL;
1186 : }
1187 :
1188 38 : ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
1189 38 : csts.raw = ctx->csts.raw;
1190 :
1191 38 : if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
1192 38 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited);
1193 38 : return 0;
1194 : }
1195 :
1196 0 : if (ms_waited < ctx->shutdown_timeout_ms) {
1197 0 : return -EAGAIN;
1198 : }
1199 :
1200 0 : NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n",
1201 : ctx->shutdown_timeout_ms);
1202 0 : if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
1203 0 : NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
1204 : }
1205 :
1206 0 : return 0;
1207 : }
1208 :
1209 : static inline uint64_t
1210 493 : nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr)
1211 : {
1212 493 : return ctrlr->cap.bits.to * 500;
1213 : }
1214 :
1215 : static void
1216 14 : nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1217 : {
1218 14 : struct spdk_nvme_ctrlr *ctrlr = ctx;
1219 :
1220 14 : if (spdk_nvme_cpl_is_error(cpl)) {
1221 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n");
1222 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1223 0 : return;
1224 : }
1225 :
1226 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
1227 : nvme_ctrlr_get_ready_timeout(ctrlr));
1228 : }
1229 :
1230 : static int
1231 21 : nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
1232 : {
1233 : union spdk_nvme_cc_register cc;
1234 : int rc;
1235 :
1236 21 : rc = nvme_transport_ctrlr_enable(ctrlr);
1237 21 : if (rc != 0) {
1238 0 : NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n");
1239 0 : return rc;
1240 : }
1241 :
1242 21 : cc.raw = ctrlr->process_init_cc.raw;
1243 21 : if (cc.bits.en != 0) {
1244 0 : NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n");
1245 0 : return -EINVAL;
1246 : }
1247 :
1248 21 : cc.bits.en = 1;
1249 21 : cc.bits.css = 0;
1250 21 : cc.bits.shn = 0;
1251 21 : cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1252 21 : cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1253 :
1254 : /* Page size is 2 ^ (12 + mps). */
1255 21 : cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1256 :
1257 : /*
1258 : * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1259 : * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1260 : * Try to support such a controller regardless.
1261 : */
1262 21 : if (ctrlr->cap.bits.css == 0) {
1263 21 : NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n");
1264 21 : ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
1265 : }
1266 :
1267 : /*
1268 : * If the user did not explicitly request a command set, or supplied a value larger than
1269 : * what can be saved in CC.CSS, use the most reasonable default.
1270 : */
1271 21 : if (ctrlr->opts.command_set >= CHAR_BIT) {
1272 0 : if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
1273 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
1274 0 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
1275 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1276 0 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
1277 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO;
1278 : } else {
1279 : /* Invalid supported bits detected, falling back to NVM. */
1280 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1281 : }
1282 : }
1283 :
1284 : /* Verify that the selected command set is supported by the controller. */
1285 21 : if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
1286 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n",
1287 : ctrlr->opts.command_set, ctrlr->cap.bits.css);
1288 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n");
1289 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1290 : }
1291 :
1292 21 : cc.bits.css = ctrlr->opts.command_set;
1293 :
1294 21 : switch (ctrlr->opts.arb_mechanism) {
1295 10 : case SPDK_NVME_CC_AMS_RR:
1296 10 : break;
1297 4 : case SPDK_NVME_CC_AMS_WRR:
1298 4 : if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
1299 2 : break;
1300 : }
1301 2 : return -EINVAL;
1302 4 : case SPDK_NVME_CC_AMS_VS:
1303 4 : if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
1304 2 : break;
1305 : }
1306 2 : return -EINVAL;
1307 3 : default:
1308 3 : return -EINVAL;
1309 : }
1310 :
1311 14 : cc.bits.ams = ctrlr->opts.arb_mechanism;
1312 14 : ctrlr->process_init_cc.raw = cc.raw;
1313 :
1314 14 : if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) {
1315 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
1316 0 : return -EIO;
1317 : }
1318 :
1319 14 : return 0;
1320 : }
1321 :
1322 : static const char *
1323 1 : nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1324 : {
1325 1 : switch (state) {
1326 0 : case NVME_CTRLR_STATE_INIT_DELAY:
1327 0 : return "delay init";
1328 0 : case NVME_CTRLR_STATE_CONNECT_ADMINQ:
1329 0 : return "connect adminq";
1330 0 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
1331 0 : return "wait for connect adminq";
1332 0 : case NVME_CTRLR_STATE_READ_VS:
1333 0 : return "read vs";
1334 0 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
1335 0 : return "read vs wait for vs";
1336 0 : case NVME_CTRLR_STATE_READ_CAP:
1337 0 : return "read cap";
1338 0 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
1339 0 : return "read cap wait for cap";
1340 0 : case NVME_CTRLR_STATE_CHECK_EN:
1341 0 : return "check en";
1342 0 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
1343 0 : return "check en wait for cc";
1344 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1345 0 : return "disable and wait for CSTS.RDY = 1";
1346 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1347 0 : return "disable and wait for CSTS.RDY = 1 reg";
1348 0 : case NVME_CTRLR_STATE_SET_EN_0:
1349 0 : return "set CC.EN = 0";
1350 0 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
1351 0 : return "set CC.EN = 0 wait for cc";
1352 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1353 0 : return "disable and wait for CSTS.RDY = 0";
1354 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
1355 0 : return "disable and wait for CSTS.RDY = 0 reg";
1356 0 : case NVME_CTRLR_STATE_DISABLED:
1357 0 : return "controller is disabled";
1358 0 : case NVME_CTRLR_STATE_ENABLE:
1359 0 : return "enable controller by writing CC.EN = 1";
1360 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
1361 0 : return "enable controller by writing CC.EN = 1 reg";
1362 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1363 0 : return "wait for CSTS.RDY = 1";
1364 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1365 0 : return "wait for CSTS.RDY = 1 reg";
1366 0 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1367 0 : return "reset admin queue";
1368 0 : case NVME_CTRLR_STATE_IDENTIFY:
1369 0 : return "identify controller";
1370 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1371 0 : return "wait for identify controller";
1372 0 : case NVME_CTRLR_STATE_CONFIGURE_AER:
1373 0 : return "configure AER";
1374 0 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1375 0 : return "wait for configure aer";
1376 0 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1377 0 : return "set keep alive timeout";
1378 0 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1379 0 : return "wait for set keep alive timeout";
1380 0 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1381 0 : return "identify controller iocs specific";
1382 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1383 0 : return "wait for identify controller iocs specific";
1384 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1385 0 : return "get zns cmd and effects log page";
1386 0 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1387 0 : return "wait for get zns cmd and effects log page";
1388 0 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1389 0 : return "set number of queues";
1390 0 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1391 0 : return "wait for set number of queues";
1392 0 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1393 0 : return "identify active ns";
1394 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1395 0 : return "wait for identify active ns";
1396 0 : case NVME_CTRLR_STATE_IDENTIFY_NS:
1397 0 : return "identify ns";
1398 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1399 0 : return "wait for identify ns";
1400 0 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1401 0 : return "identify namespace id descriptors";
1402 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1403 0 : return "wait for identify namespace id descriptors";
1404 0 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1405 0 : return "identify ns iocs specific";
1406 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1407 0 : return "wait for identify ns iocs specific";
1408 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1409 0 : return "set supported log pages";
1410 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
1411 0 : return "set supported INTEL log pages";
1412 0 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
1413 0 : return "wait for supported INTEL log pages";
1414 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1415 0 : return "set supported features";
1416 0 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1417 0 : return "set doorbell buffer config";
1418 0 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1419 0 : return "wait for doorbell buffer config";
1420 0 : case NVME_CTRLR_STATE_SET_HOST_ID:
1421 0 : return "set host ID";
1422 0 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1423 0 : return "wait for set host ID";
1424 0 : case NVME_CTRLR_STATE_TRANSPORT_READY:
1425 0 : return "transport ready";
1426 0 : case NVME_CTRLR_STATE_READY:
1427 0 : return "ready";
1428 1 : case NVME_CTRLR_STATE_ERROR:
1429 1 : return "error";
1430 0 : case NVME_CTRLR_STATE_DISCONNECTED:
1431 0 : return "disconnected";
1432 : }
1433 0 : return "unknown";
1434 : };
1435 :
1436 : static void
1437 714 : _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1438 : uint64_t timeout_in_ms, bool quiet)
1439 : {
1440 : uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1441 :
1442 714 : ctrlr->state = state;
1443 714 : if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
1444 33 : if (!quiet) {
1445 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
1446 : nvme_ctrlr_state_string(ctrlr->state));
1447 : }
1448 33 : return;
1449 : }
1450 :
1451 681 : if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1452 679 : goto inf;
1453 : }
1454 :
1455 2 : ticks_per_ms = spdk_get_ticks_hz() / 1000;
1456 2 : if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1457 0 : NVME_CTRLR_ERRLOG(ctrlr,
1458 : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1459 0 : goto inf;
1460 : }
1461 :
1462 2 : now_ticks = spdk_get_ticks();
1463 2 : timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1464 2 : if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1465 1 : NVME_CTRLR_ERRLOG(ctrlr,
1466 : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1467 1 : goto inf;
1468 : }
1469 :
1470 1 : ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1471 1 : if (!quiet) {
1472 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
1473 : nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1474 : }
1475 1 : return;
1476 680 : inf:
1477 680 : if (!quiet) {
1478 680 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
1479 : nvme_ctrlr_state_string(ctrlr->state));
1480 : }
1481 680 : ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1482 : }
1483 :
1484 : static void
1485 681 : nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1486 : uint64_t timeout_in_ms)
1487 : {
1488 681 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
1489 681 : }
1490 :
1491 : static void
1492 33 : nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1493 : uint64_t timeout_in_ms)
1494 : {
1495 33 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
1496 33 : }
1497 :
1498 : static void
1499 47 : nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1500 : {
1501 47 : spdk_free(ctrlr->cdata_zns);
1502 47 : ctrlr->cdata_zns = NULL;
1503 47 : }
1504 :
1505 : static void
1506 47 : nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1507 : {
1508 47 : nvme_ctrlr_free_zns_specific_data(ctrlr);
1509 47 : }
1510 :
1511 : static void
1512 48 : nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1513 : {
1514 48 : if (ctrlr->shadow_doorbell) {
1515 1 : spdk_free(ctrlr->shadow_doorbell);
1516 1 : ctrlr->shadow_doorbell = NULL;
1517 : }
1518 :
1519 48 : if (ctrlr->eventidx) {
1520 1 : spdk_free(ctrlr->eventidx);
1521 1 : ctrlr->eventidx = NULL;
1522 : }
1523 48 : }
1524 :
1525 : static void
1526 1 : nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1527 : {
1528 1 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1529 :
1530 1 : if (spdk_nvme_cpl_is_error(cpl)) {
1531 0 : NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n");
1532 : } else {
1533 1 : NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n");
1534 : }
1535 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1536 1 : ctrlr->opts.admin_timeout_ms);
1537 1 : }
1538 :
1539 : static int
1540 15 : nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1541 : {
1542 15 : int rc = 0;
1543 15 : uint64_t prp1, prp2, len;
1544 :
1545 15 : if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
1546 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1547 14 : ctrlr->opts.admin_timeout_ms);
1548 14 : return 0;
1549 : }
1550 :
1551 1 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
1552 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1553 0 : ctrlr->opts.admin_timeout_ms);
1554 0 : return 0;
1555 : }
1556 :
1557 : /* only 1 page size for doorbell buffer */
1558 1 : ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1559 : NULL, SPDK_ENV_LCORE_ID_ANY,
1560 : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1561 1 : if (ctrlr->shadow_doorbell == NULL) {
1562 0 : rc = -ENOMEM;
1563 0 : goto error;
1564 : }
1565 :
1566 1 : len = ctrlr->page_size;
1567 1 : prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1568 1 : if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1569 0 : rc = -EFAULT;
1570 0 : goto error;
1571 : }
1572 :
1573 1 : ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1574 : NULL, SPDK_ENV_LCORE_ID_ANY,
1575 : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1576 1 : if (ctrlr->eventidx == NULL) {
1577 0 : rc = -ENOMEM;
1578 0 : goto error;
1579 : }
1580 :
1581 1 : len = ctrlr->page_size;
1582 1 : prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1583 1 : if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1584 0 : rc = -EFAULT;
1585 0 : goto error;
1586 : }
1587 :
1588 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1589 1 : ctrlr->opts.admin_timeout_ms);
1590 :
1591 1 : rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1592 : nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1593 1 : if (rc != 0) {
1594 0 : goto error;
1595 : }
1596 :
1597 1 : return 0;
1598 :
1599 0 : error:
1600 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1601 0 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1602 0 : return rc;
1603 : }
1604 :
1605 : void
1606 47 : nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1607 : {
1608 : struct nvme_request *req, *tmp;
1609 47 : struct spdk_nvme_cpl cpl = {};
1610 :
1611 47 : cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1612 47 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1613 :
1614 47 : STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
1615 0 : STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
1616 0 : ctrlr->outstanding_aborts++;
1617 :
1618 0 : nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
1619 : }
1620 47 : }
1621 :
1622 : static int
1623 2 : nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1624 : {
1625 2 : if (ctrlr->is_resetting || ctrlr->is_removed) {
1626 : /*
1627 : * Controller is already resetting or has been removed. Return
1628 : * immediately since there is no need to kick off another
1629 : * reset in these cases.
1630 : */
1631 1 : return ctrlr->is_resetting ? -EBUSY : -ENXIO;
1632 : }
1633 :
1634 1 : ctrlr->is_resetting = true;
1635 1 : ctrlr->is_failed = false;
1636 1 : ctrlr->is_disconnecting = true;
1637 1 : ctrlr->prepare_for_reset = true;
1638 :
1639 1 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n");
1640 :
1641 : /* Disable keep-alive, it'll be re-enabled as part of the init process */
1642 1 : ctrlr->keep_alive_interval_ticks = 0;
1643 :
1644 : /* Abort all of the queued abort requests */
1645 1 : nvme_ctrlr_abort_queued_aborts(ctrlr);
1646 :
1647 1 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1648 :
1649 1 : ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1650 1 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1651 :
1652 1 : return 0;
1653 : }
1654 :
1655 : static void
1656 1 : nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr)
1657 : {
1658 1 : assert(ctrlr->is_failed == false);
1659 1 : ctrlr->is_disconnecting = false;
1660 :
1661 : /* Doorbell buffer config is invalid during reset */
1662 1 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1663 :
1664 : /* I/O Command Set Specific Identify Controller data is invalidated during reset */
1665 1 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
1666 :
1667 1 : spdk_bit_array_free(&ctrlr->free_io_qids);
1668 :
1669 : /* Set the state back to DISCONNECTED to cause a full hardware reset. */
1670 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE);
1671 1 : }
1672 :
1673 : int
1674 0 : spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1675 : {
1676 : int rc;
1677 :
1678 0 : nvme_ctrlr_lock(ctrlr);
1679 0 : rc = nvme_ctrlr_disconnect(ctrlr);
1680 0 : nvme_ctrlr_unlock(ctrlr);
1681 :
1682 0 : return rc;
1683 : }
1684 :
1685 : void
1686 1 : spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr)
1687 : {
1688 1 : nvme_ctrlr_lock(ctrlr);
1689 :
1690 1 : ctrlr->prepare_for_reset = false;
1691 :
1692 : /* Set the state back to INIT to cause a full hardware reset. */
1693 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1694 :
1695 : /* Return without releasing ctrlr_lock. ctrlr_lock will be released when
1696 : * spdk_nvme_ctrlr_reset_poll_async() returns 0.
1697 : */
1698 1 : }
1699 :
1700 : int
1701 0 : nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1702 : {
1703 : bool async;
1704 : int rc;
1705 :
1706 0 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc ||
1707 0 : spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) {
1708 0 : assert(false);
1709 : return -EINVAL;
1710 : }
1711 :
1712 : /* Force a synchronous connect. */
1713 0 : async = qpair->async;
1714 0 : qpair->async = false;
1715 0 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1716 0 : qpair->async = async;
1717 :
1718 0 : if (rc != 0) {
1719 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1720 : }
1721 :
1722 0 : return rc;
1723 : }
1724 :
1725 : /**
1726 : * This function will be called when the controller is being reinitialized.
1727 : * Note: the ctrlr_lock must be held when calling this function.
1728 : */
1729 : int
1730 24 : spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr)
1731 : {
1732 : struct spdk_nvme_ns *ns, *tmp_ns;
1733 : struct spdk_nvme_qpair *qpair;
1734 24 : int rc = 0, rc_tmp = 0;
1735 :
1736 24 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1737 0 : NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n");
1738 0 : rc = -1;
1739 : }
1740 24 : if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) {
1741 23 : return -EAGAIN;
1742 : }
1743 :
1744 : /*
1745 : * For non-fabrics controllers, the memory locations of the transport qpair
1746 : * don't change when the controller is reset. They simply need to be
1747 : * re-enabled with admin commands to the controller. For fabric
1748 : * controllers we need to disconnect and reconnect the qpair on its
1749 : * own thread outside of the context of the reset.
1750 : */
1751 1 : if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
1752 : /* Reinitialize qpairs */
1753 1 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1754 : /* Always clear the qid bit here, even for a foreign qpair. We need
1755 : * to make sure another process doesn't get the chance to grab that
1756 : * qid.
1757 : */
1758 0 : assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
1759 0 : spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
1760 0 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) {
1761 : /*
1762 : * We cannot reinitialize a foreign qpair. The qpair's owning
1763 : * process will take care of it. Set failure reason to FAILURE_RESET
1764 : * to ensure that happens.
1765 : */
1766 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET;
1767 0 : continue;
1768 : }
1769 0 : rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair);
1770 0 : if (rc_tmp != 0) {
1771 0 : rc = rc_tmp;
1772 : }
1773 : }
1774 : }
1775 :
1776 : /*
1777 : * Take this opportunity to remove inactive namespaces. During a reset namespace
1778 : * handles can be invalidated.
1779 : */
1780 5 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
1781 4 : if (!ns->active) {
1782 1 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
1783 1 : spdk_free(ns);
1784 : }
1785 : }
1786 :
1787 1 : if (rc) {
1788 0 : nvme_ctrlr_fail(ctrlr, false);
1789 : }
1790 1 : ctrlr->is_resetting = false;
1791 :
1792 1 : nvme_ctrlr_unlock(ctrlr);
1793 :
1794 1 : if (!ctrlr->cdata.oaes.ns_attribute_notices) {
1795 : /*
1796 : * If controller doesn't support ns_attribute_notices and
1797 : * namespace attributes change (e.g. number of namespaces)
1798 : * we need to update system handling device reset.
1799 : */
1800 1 : nvme_io_msg_ctrlr_update(ctrlr);
1801 : }
1802 :
1803 1 : return rc;
1804 : }
1805 :
1806 : /*
1807 : * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset
1808 : * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair.
1809 : * The following two functions are added to do a Controller Level Reset. They have
1810 : * to be called under the nvme controller's lock.
1811 : */
1812 : void
1813 1 : nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1814 : {
1815 1 : assert(ctrlr->is_disconnecting == true);
1816 :
1817 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
1818 1 : }
1819 :
1820 : int
1821 2 : nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr)
1822 : {
1823 2 : int rc = 0;
1824 :
1825 2 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1826 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n");
1827 0 : rc = -1;
1828 : }
1829 :
1830 2 : if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) {
1831 1 : return -EAGAIN;
1832 : }
1833 :
1834 1 : return rc;
1835 : }
1836 :
1837 : static void
1838 1 : nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1839 : {
1840 : struct spdk_nvme_qpair *qpair;
1841 :
1842 1 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1843 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1844 : }
1845 1 : }
1846 :
1847 : int
1848 2 : spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1849 : {
1850 : int rc;
1851 :
1852 2 : nvme_ctrlr_lock(ctrlr);
1853 :
1854 2 : rc = nvme_ctrlr_disconnect(ctrlr);
1855 2 : if (rc == 0) {
1856 1 : nvme_ctrlr_fail_io_qpairs(ctrlr);
1857 : }
1858 :
1859 2 : nvme_ctrlr_unlock(ctrlr);
1860 :
1861 2 : if (rc != 0) {
1862 1 : if (rc == -EBUSY) {
1863 1 : rc = 0;
1864 : }
1865 1 : return rc;
1866 : }
1867 :
1868 : while (1) {
1869 1 : rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr);
1870 1 : if (rc == -ENXIO) {
1871 1 : break;
1872 : }
1873 : }
1874 :
1875 1 : spdk_nvme_ctrlr_reconnect_async(ctrlr);
1876 :
1877 : while (true) {
1878 24 : rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr);
1879 24 : if (rc != -EAGAIN) {
1880 1 : break;
1881 : }
1882 : }
1883 :
1884 1 : return rc;
1885 : }
1886 :
1887 : int
1888 0 : spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1889 : {
1890 : union spdk_nvme_cap_register cap;
1891 0 : int rc = 0;
1892 :
1893 0 : cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1894 0 : if (cap.bits.nssrs == 0) {
1895 0 : NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n");
1896 0 : return -ENOTSUP;
1897 : }
1898 :
1899 0 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n");
1900 0 : nvme_ctrlr_lock(ctrlr);
1901 0 : ctrlr->is_resetting = true;
1902 0 : rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1903 0 : ctrlr->is_resetting = false;
1904 :
1905 0 : nvme_ctrlr_unlock(ctrlr);
1906 : /*
1907 : * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1908 : * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1909 : */
1910 0 : return rc;
1911 : }
1912 :
1913 : int
1914 4 : spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
1915 : {
1916 4 : int rc = 0;
1917 :
1918 4 : nvme_ctrlr_lock(ctrlr);
1919 :
1920 4 : if (ctrlr->is_failed == false) {
1921 1 : rc = -EPERM;
1922 1 : goto out;
1923 : }
1924 :
1925 3 : if (trid->trtype != ctrlr->trid.trtype) {
1926 1 : rc = -EINVAL;
1927 1 : goto out;
1928 : }
1929 :
1930 2 : if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
1931 1 : rc = -EINVAL;
1932 1 : goto out;
1933 : }
1934 :
1935 1 : ctrlr->trid = *trid;
1936 :
1937 4 : out:
1938 4 : nvme_ctrlr_unlock(ctrlr);
1939 4 : return rc;
1940 : }
1941 :
1942 : void
1943 0 : spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
1944 : spdk_nvme_remove_cb remove_cb, void *remove_ctx)
1945 : {
1946 0 : if (!spdk_process_is_primary()) {
1947 0 : return;
1948 : }
1949 :
1950 0 : nvme_ctrlr_lock(ctrlr);
1951 0 : ctrlr->remove_cb = remove_cb;
1952 0 : ctrlr->cb_ctx = remove_ctx;
1953 0 : nvme_ctrlr_unlock(ctrlr);
1954 : }
1955 :
1956 : static void
1957 16 : nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
1958 : {
1959 16 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1960 :
1961 16 : if (spdk_nvme_cpl_is_error(cpl)) {
1962 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n");
1963 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1964 0 : return;
1965 : }
1966 :
1967 : /*
1968 : * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
1969 : * controller supports.
1970 : */
1971 16 : ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
1972 16 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
1973 16 : if (ctrlr->cdata.mdts > 0) {
1974 0 : ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
1975 : ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
1976 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
1977 : }
1978 :
1979 16 : NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
1980 16 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
1981 1 : ctrlr->cntlid = ctrlr->cdata.cntlid;
1982 : } else {
1983 : /*
1984 : * Fabrics controllers should already have CNTLID from the Connect command.
1985 : *
1986 : * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
1987 : * trust the one from Connect.
1988 : */
1989 15 : if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
1990 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
1991 : ctrlr->cdata.cntlid, ctrlr->cntlid);
1992 : }
1993 : }
1994 :
1995 16 : if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
1996 0 : assert(ctrlr->cdata.sgls.supported != 0x3);
1997 0 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
1998 0 : if (ctrlr->cdata.sgls.supported == 0x2) {
1999 0 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
2000 : }
2001 :
2002 0 : ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
2003 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges);
2004 : }
2005 :
2006 16 : if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2007 0 : ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED;
2008 : }
2009 :
2010 16 : if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
2011 0 : ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
2012 : }
2013 :
2014 16 : if (ctrlr->cdata.oacs.directives) {
2015 0 : ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
2016 : }
2017 :
2018 16 : NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n",
2019 : ctrlr->cdata.fuses.compare_and_write);
2020 16 : if (ctrlr->cdata.fuses.compare_and_write) {
2021 0 : ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
2022 : }
2023 :
2024 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2025 16 : ctrlr->opts.admin_timeout_ms);
2026 : }
2027 :
2028 : static int
2029 16 : nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
2030 : {
2031 : int rc;
2032 :
2033 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
2034 16 : ctrlr->opts.admin_timeout_ms);
2035 :
2036 16 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
2037 16 : &ctrlr->cdata, sizeof(ctrlr->cdata),
2038 : nvme_ctrlr_identify_done, ctrlr);
2039 16 : if (rc != 0) {
2040 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2041 0 : return rc;
2042 : }
2043 :
2044 16 : return 0;
2045 : }
2046 :
2047 : static void
2048 0 : nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
2049 : {
2050 : struct spdk_nvme_cmds_and_effect_log_page *log_page;
2051 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
2052 :
2053 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2054 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
2055 0 : spdk_free(ctrlr->tmp_ptr);
2056 0 : ctrlr->tmp_ptr = NULL;
2057 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2058 0 : return;
2059 : }
2060 :
2061 0 : log_page = ctrlr->tmp_ptr;
2062 :
2063 0 : if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
2064 0 : ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
2065 : }
2066 0 : spdk_free(ctrlr->tmp_ptr);
2067 0 : ctrlr->tmp_ptr = NULL;
2068 :
2069 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
2070 : }
2071 :
2072 : static int
2073 0 : nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
2074 : {
2075 : int rc;
2076 :
2077 0 : assert(!ctrlr->tmp_ptr);
2078 0 : ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
2079 : SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2080 0 : if (!ctrlr->tmp_ptr) {
2081 0 : rc = -ENOMEM;
2082 0 : goto error;
2083 : }
2084 :
2085 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
2086 0 : ctrlr->opts.admin_timeout_ms);
2087 :
2088 0 : rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
2089 : 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
2090 : 0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
2091 : nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
2092 0 : if (rc != 0) {
2093 0 : goto error;
2094 : }
2095 :
2096 0 : return 0;
2097 :
2098 0 : error:
2099 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2100 0 : spdk_free(ctrlr->tmp_ptr);
2101 0 : ctrlr->tmp_ptr = NULL;
2102 0 : return rc;
2103 : }
2104 :
2105 : static void
2106 0 : nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
2107 : {
2108 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2109 :
2110 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2111 : /* no need to print an error, the controller simply does not support ZNS */
2112 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2113 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2114 0 : ctrlr->opts.admin_timeout_ms);
2115 0 : return;
2116 : }
2117 :
2118 : /* A zero zasl value means use mdts */
2119 0 : if (ctrlr->cdata_zns->zasl) {
2120 0 : uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
2121 0 : ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
2122 : } else {
2123 0 : ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
2124 : }
2125 :
2126 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
2127 0 : ctrlr->opts.admin_timeout_ms);
2128 : }
2129 :
2130 : /**
2131 : * This function will try to fetch the I/O Command Specific Controller data structure for
2132 : * each I/O Command Set supported by SPDK.
2133 : *
2134 : * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
2135 : * will be returned. Since we are fetching in a exploratively way, getting an error back
2136 : * from the controller should not be treated as fatal.
2137 : *
2138 : * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
2139 : *
2140 : * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
2141 : * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
2142 : */
2143 : static int
2144 19 : nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2145 : {
2146 : int rc;
2147 :
2148 19 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2149 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2150 19 : ctrlr->opts.admin_timeout_ms);
2151 19 : return 0;
2152 : }
2153 :
2154 : /*
2155 : * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
2156 : * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
2157 : * which would require additional functions and complexity for no good reason.
2158 : */
2159 0 : assert(!ctrlr->cdata_zns);
2160 0 : ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2161 : SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2162 0 : if (!ctrlr->cdata_zns) {
2163 0 : rc = -ENOMEM;
2164 0 : goto error;
2165 : }
2166 :
2167 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
2168 0 : ctrlr->opts.admin_timeout_ms);
2169 :
2170 0 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
2171 0 : ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
2172 : nvme_ctrlr_identify_zns_specific_done, ctrlr);
2173 0 : if (rc != 0) {
2174 0 : goto error;
2175 : }
2176 :
2177 0 : return 0;
2178 :
2179 0 : error:
2180 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2181 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2182 0 : return rc;
2183 : }
2184 :
2185 : enum nvme_active_ns_state {
2186 : NVME_ACTIVE_NS_STATE_IDLE,
2187 : NVME_ACTIVE_NS_STATE_PROCESSING,
2188 : NVME_ACTIVE_NS_STATE_DONE,
2189 : NVME_ACTIVE_NS_STATE_ERROR
2190 : };
2191 :
2192 : typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
2193 :
2194 : struct nvme_active_ns_ctx {
2195 : struct spdk_nvme_ctrlr *ctrlr;
2196 : uint32_t page_count;
2197 : uint32_t next_nsid;
2198 : uint32_t *new_ns_list;
2199 : nvme_active_ns_ctx_deleter deleter;
2200 :
2201 : enum nvme_active_ns_state state;
2202 : };
2203 :
2204 : static struct nvme_active_ns_ctx *
2205 45 : nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
2206 : {
2207 : struct nvme_active_ns_ctx *ctx;
2208 45 : uint32_t *new_ns_list = NULL;
2209 :
2210 45 : ctx = calloc(1, sizeof(*ctx));
2211 45 : if (!ctx) {
2212 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n");
2213 0 : return NULL;
2214 : }
2215 :
2216 45 : new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
2217 : NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE);
2218 45 : if (!new_ns_list) {
2219 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n");
2220 0 : free(ctx);
2221 0 : return NULL;
2222 : }
2223 :
2224 45 : ctx->page_count = 1;
2225 45 : ctx->new_ns_list = new_ns_list;
2226 45 : ctx->ctrlr = ctrlr;
2227 45 : ctx->deleter = deleter;
2228 :
2229 45 : return ctx;
2230 : }
2231 :
2232 : static void
2233 45 : nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
2234 : {
2235 45 : spdk_free(ctx->new_ns_list);
2236 45 : free(ctx);
2237 45 : }
2238 :
2239 : static int
2240 18403 : nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2241 : {
2242 18403 : struct spdk_nvme_ns tmp, *ns;
2243 :
2244 18403 : assert(ctrlr != NULL);
2245 :
2246 18403 : tmp.id = nsid;
2247 18403 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
2248 18403 : if (ns == NULL) {
2249 0 : return -EINVAL;
2250 : }
2251 :
2252 18403 : nvme_ns_destruct(ns);
2253 18403 : ns->active = false;
2254 :
2255 18403 : return 0;
2256 : }
2257 :
2258 : static int
2259 12311 : nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2260 : {
2261 : struct spdk_nvme_ns *ns;
2262 :
2263 12311 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
2264 0 : return -EINVAL;
2265 : }
2266 :
2267 : /* Namespaces are constructed on demand, so simply request it. */
2268 12311 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2269 12311 : if (ns == NULL) {
2270 0 : return -ENOMEM;
2271 : }
2272 :
2273 12311 : ns->active = true;
2274 :
2275 12311 : return 0;
2276 : }
2277 :
2278 : static void
2279 44 : nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list,
2280 : size_t max_entries)
2281 : {
2282 44 : uint32_t active_ns_count = 0;
2283 : size_t i;
2284 : uint32_t nsid;
2285 : struct spdk_nvme_ns *ns, *tmp_ns;
2286 : int rc;
2287 :
2288 : /* First, remove namespaces that no longer exist */
2289 15387 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
2290 15343 : nsid = new_ns_list[0];
2291 15343 : active_ns_count = 0;
2292 3547429 : while (nsid != 0) {
2293 3536712 : if (nsid == ns->id) {
2294 4626 : break;
2295 : }
2296 :
2297 3532086 : nsid = new_ns_list[active_ns_count++];
2298 : }
2299 :
2300 15343 : if (nsid != ns->id) {
2301 : /* Did not find this namespace id in the new list. */
2302 10717 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id);
2303 10717 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
2304 : }
2305 : }
2306 :
2307 : /* Next, add new namespaces */
2308 44 : active_ns_count = 0;
2309 12355 : for (i = 0; i < max_entries; i++) {
2310 12355 : nsid = new_ns_list[active_ns_count];
2311 :
2312 12355 : if (nsid == 0) {
2313 44 : break;
2314 : }
2315 :
2316 : /* If the namespace already exists, this will not construct it a second time. */
2317 12311 : rc = nvme_ctrlr_construct_namespace(ctrlr, nsid);
2318 12311 : if (rc != 0) {
2319 : /* We can't easily handle a failure here. But just move on. */
2320 0 : assert(false);
2321 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n");
2322 : continue;
2323 : }
2324 :
2325 12311 : active_ns_count++;
2326 : }
2327 :
2328 44 : ctrlr->active_ns_count = active_ns_count;
2329 44 : }
2330 :
2331 : static void
2332 30 : nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2333 : {
2334 30 : struct nvme_active_ns_ctx *ctx = arg;
2335 30 : uint32_t *new_ns_list = NULL;
2336 :
2337 30 : if (spdk_nvme_cpl_is_error(cpl)) {
2338 1 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2339 1 : goto out;
2340 : }
2341 :
2342 29 : ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1];
2343 29 : if (ctx->next_nsid == 0) {
2344 24 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2345 24 : goto out;
2346 : }
2347 :
2348 5 : ctx->page_count++;
2349 5 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2350 5 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2351 5 : ctx->ctrlr->page_size);
2352 5 : if (!new_ns_list) {
2353 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2354 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2355 0 : goto out;
2356 : }
2357 :
2358 5 : ctx->new_ns_list = new_ns_list;
2359 5 : nvme_ctrlr_identify_active_ns_async(ctx);
2360 5 : return;
2361 :
2362 25 : out:
2363 25 : if (ctx->deleter) {
2364 9 : ctx->deleter(ctx);
2365 : }
2366 : }
2367 :
2368 : static void
2369 50 : nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
2370 : {
2371 50 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2372 : uint32_t i;
2373 : int rc;
2374 :
2375 50 : if (ctrlr->cdata.nn == 0) {
2376 16 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2377 16 : goto out;
2378 : }
2379 :
2380 34 : assert(ctx->new_ns_list != NULL);
2381 :
2382 : /*
2383 : * If controller doesn't support active ns list CNS 0x02 dummy up
2384 : * an active ns list, i.e. all namespaces report as active
2385 : */
2386 34 : if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
2387 : uint32_t *new_ns_list;
2388 :
2389 : /*
2390 : * Active NS list must always end with zero element.
2391 : * So, we allocate for cdata.nn+1.
2392 : */
2393 4 : ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1,
2394 : sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0]));
2395 4 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2396 4 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2397 4 : ctx->ctrlr->page_size);
2398 4 : if (!new_ns_list) {
2399 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2400 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2401 0 : goto out;
2402 : }
2403 :
2404 4 : ctx->new_ns_list = new_ns_list;
2405 4 : ctx->new_ns_list[ctrlr->cdata.nn] = 0;
2406 4091 : for (i = 0; i < ctrlr->cdata.nn; i++) {
2407 4087 : ctx->new_ns_list[i] = i + 1;
2408 : }
2409 :
2410 4 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2411 4 : goto out;
2412 : }
2413 :
2414 30 : ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
2415 30 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
2416 30 : &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list),
2417 : nvme_ctrlr_identify_active_ns_async_done, ctx);
2418 30 : if (rc != 0) {
2419 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2420 0 : goto out;
2421 : }
2422 :
2423 30 : return;
2424 :
2425 20 : out:
2426 20 : if (ctx->deleter) {
2427 15 : ctx->deleter(ctx);
2428 : }
2429 : }
2430 :
2431 : static void
2432 24 : _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
2433 : {
2434 24 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2435 : struct spdk_nvme_ns *ns;
2436 :
2437 24 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2438 0 : nvme_active_ns_ctx_destroy(ctx);
2439 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2440 0 : return;
2441 : }
2442 :
2443 24 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2444 :
2445 28 : RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) {
2446 4 : nvme_ns_free_iocs_specific_data(ns);
2447 : }
2448 :
2449 24 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2450 24 : nvme_active_ns_ctx_destroy(ctx);
2451 24 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
2452 : }
2453 :
2454 : static void
2455 24 : _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2456 : {
2457 : struct nvme_active_ns_ctx *ctx;
2458 :
2459 24 : ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
2460 24 : if (!ctx) {
2461 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2462 0 : return;
2463 : }
2464 :
2465 24 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
2466 24 : ctrlr->opts.admin_timeout_ms);
2467 24 : nvme_ctrlr_identify_active_ns_async(ctx);
2468 : }
2469 :
2470 : int
2471 21 : nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2472 : {
2473 : struct nvme_active_ns_ctx *ctx;
2474 : int rc;
2475 :
2476 21 : ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
2477 21 : if (!ctx) {
2478 0 : return -ENOMEM;
2479 : }
2480 :
2481 21 : nvme_ctrlr_identify_active_ns_async(ctx);
2482 21 : while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
2483 0 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
2484 0 : if (rc < 0) {
2485 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2486 0 : break;
2487 : }
2488 : }
2489 :
2490 21 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2491 1 : nvme_active_ns_ctx_destroy(ctx);
2492 1 : return -ENXIO;
2493 : }
2494 :
2495 20 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2496 20 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2497 20 : nvme_active_ns_ctx_destroy(ctx);
2498 :
2499 20 : return 0;
2500 : }
2501 :
2502 : static void
2503 21 : nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2504 : {
2505 21 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2506 21 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2507 : uint32_t nsid;
2508 : int rc;
2509 :
2510 21 : if (spdk_nvme_cpl_is_error(cpl)) {
2511 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2512 0 : return;
2513 : }
2514 :
2515 21 : nvme_ns_set_identify_data(ns);
2516 :
2517 : /* move on to the next active NS */
2518 21 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2519 21 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2520 21 : if (ns == NULL) {
2521 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2522 6 : ctrlr->opts.admin_timeout_ms);
2523 6 : return;
2524 : }
2525 15 : ns->ctrlr = ctrlr;
2526 15 : ns->id = nsid;
2527 :
2528 15 : rc = nvme_ctrlr_identify_ns_async(ns);
2529 15 : if (rc) {
2530 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2531 : }
2532 : }
2533 :
2534 : static int
2535 21 : nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
2536 : {
2537 21 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2538 : struct spdk_nvme_ns_data *nsdata;
2539 :
2540 21 : nsdata = &ns->nsdata;
2541 :
2542 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
2543 21 : ctrlr->opts.admin_timeout_ms);
2544 21 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
2545 : nsdata, sizeof(*nsdata),
2546 : nvme_ctrlr_identify_ns_async_done, ns);
2547 : }
2548 :
2549 : static int
2550 14 : nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2551 : {
2552 : uint32_t nsid;
2553 : struct spdk_nvme_ns *ns;
2554 : int rc;
2555 :
2556 14 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2557 14 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2558 14 : if (ns == NULL) {
2559 : /* No active NS, move on to the next state */
2560 8 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2561 8 : ctrlr->opts.admin_timeout_ms);
2562 8 : return 0;
2563 : }
2564 :
2565 6 : ns->ctrlr = ctrlr;
2566 6 : ns->id = nsid;
2567 :
2568 6 : rc = nvme_ctrlr_identify_ns_async(ns);
2569 6 : if (rc) {
2570 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2571 : }
2572 :
2573 6 : return rc;
2574 : }
2575 :
2576 : static int
2577 4 : nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2578 : {
2579 : uint32_t nsid;
2580 : struct spdk_nvme_ns *ns;
2581 : int rc;
2582 :
2583 4 : if (!prev_nsid) {
2584 2 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2585 : } else {
2586 : /* move on to the next active NS */
2587 2 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2588 : }
2589 :
2590 4 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2591 4 : if (ns == NULL) {
2592 : /* No first/next active NS, move on to the next state */
2593 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2594 1 : ctrlr->opts.admin_timeout_ms);
2595 1 : return 0;
2596 : }
2597 :
2598 : /* loop until we find a ns which has (supported) iocs specific data */
2599 10 : while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2600 8 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2601 8 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2602 8 : if (ns == NULL) {
2603 : /* no namespace with (supported) iocs specific data found */
2604 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2605 1 : ctrlr->opts.admin_timeout_ms);
2606 1 : return 0;
2607 : }
2608 : }
2609 :
2610 2 : rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2611 2 : if (rc) {
2612 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2613 : }
2614 :
2615 2 : return rc;
2616 : }
2617 :
2618 : static void
2619 0 : nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2620 : {
2621 0 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2622 0 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2623 :
2624 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2625 0 : nvme_ns_free_zns_specific_data(ns);
2626 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2627 0 : return;
2628 : }
2629 :
2630 0 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2631 : }
2632 :
2633 : static int
2634 2 : nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2635 : {
2636 2 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2637 : int rc;
2638 :
2639 2 : switch (ns->csi) {
2640 2 : case SPDK_NVME_CSI_ZNS:
2641 2 : break;
2642 0 : default:
2643 : /*
2644 : * This switch must handle all cases for which
2645 : * nvme_ns_has_supported_iocs_specific_data() returns true,
2646 : * other cases should never happen.
2647 : */
2648 0 : assert(0);
2649 : }
2650 :
2651 2 : assert(!ns->nsdata_zns);
2652 2 : ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2653 : SPDK_MALLOC_SHARE);
2654 2 : if (!ns->nsdata_zns) {
2655 0 : return -ENOMEM;
2656 : }
2657 :
2658 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2659 2 : ctrlr->opts.admin_timeout_ms);
2660 2 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
2661 2 : ns->nsdata_zns, sizeof(*ns->nsdata_zns),
2662 : nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2663 2 : if (rc) {
2664 1 : nvme_ns_free_zns_specific_data(ns);
2665 : }
2666 :
2667 2 : return rc;
2668 : }
2669 :
2670 : static int
2671 14 : nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2672 : {
2673 14 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2674 : /* Multi IOCS not supported/enabled, move on to the next state */
2675 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2676 14 : ctrlr->opts.admin_timeout_ms);
2677 14 : return 0;
2678 : }
2679 :
2680 0 : return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2681 : }
2682 :
2683 : static void
2684 6 : nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2685 : {
2686 6 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2687 6 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2688 : uint32_t nsid;
2689 : int rc;
2690 :
2691 6 : if (spdk_nvme_cpl_is_error(cpl)) {
2692 : /*
2693 : * Many controllers claim to be compatible with NVMe 1.3, however,
2694 : * they do not implement NS ID Desc List. Therefore, instead of setting
2695 : * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion
2696 : * error and move on to the next state.
2697 : *
2698 : * The proper way is to create a new quirk for controllers that violate
2699 : * the NVMe 1.3 spec by not supporting NS ID Desc List.
2700 : * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since
2701 : * it is too generic and was added in order to handle controllers that
2702 : * violate the NVMe 1.1 spec by not supporting ACTIVE LIST).
2703 : */
2704 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2705 0 : ctrlr->opts.admin_timeout_ms);
2706 0 : return;
2707 : }
2708 :
2709 6 : nvme_ns_set_id_desc_list_data(ns);
2710 :
2711 : /* move on to the next active NS */
2712 6 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2713 6 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2714 6 : if (ns == NULL) {
2715 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2716 2 : ctrlr->opts.admin_timeout_ms);
2717 2 : return;
2718 : }
2719 :
2720 4 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2721 4 : if (rc) {
2722 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2723 : }
2724 : }
2725 :
2726 : static int
2727 6 : nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2728 : {
2729 6 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2730 :
2731 6 : memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2732 :
2733 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2734 6 : ctrlr->opts.admin_timeout_ms);
2735 12 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2736 6 : 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
2737 : nvme_ctrlr_identify_id_desc_async_done, ns);
2738 : }
2739 :
2740 : static int
2741 14 : nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2742 : {
2743 : uint32_t nsid;
2744 : struct spdk_nvme_ns *ns;
2745 : int rc;
2746 :
2747 14 : if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
2748 12 : !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
2749 2 : (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2750 12 : NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
2751 : /* NS ID Desc List not supported, move on to the next state */
2752 12 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2753 12 : ctrlr->opts.admin_timeout_ms);
2754 12 : return 0;
2755 : }
2756 :
2757 2 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2758 2 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2759 2 : if (ns == NULL) {
2760 : /* No active NS, move on to the next state */
2761 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2762 0 : ctrlr->opts.admin_timeout_ms);
2763 0 : return 0;
2764 : }
2765 :
2766 2 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2767 2 : if (rc) {
2768 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2769 : }
2770 :
2771 2 : return rc;
2772 : }
2773 :
2774 : static void
2775 19 : nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2776 : {
2777 19 : if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
2778 4 : if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
2779 0 : NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n",
2780 : ctrlr->cdata.nvmf_specific.ioccsz);
2781 0 : ctrlr->cdata.nvmf_specific.ioccsz = 4;
2782 0 : assert(0);
2783 : }
2784 4 : ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
2785 4 : ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
2786 : }
2787 19 : }
2788 :
2789 : static void
2790 19 : nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2791 : {
2792 : uint32_t cq_allocated, sq_allocated, min_allocated, i;
2793 19 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2794 :
2795 19 : if (spdk_nvme_cpl_is_error(cpl)) {
2796 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n");
2797 0 : ctrlr->opts.num_io_queues = 0;
2798 : } else {
2799 : /*
2800 : * Data in cdw0 is 0-based.
2801 : * Lower 16-bits indicate number of submission queues allocated.
2802 : * Upper 16-bits indicate number of completion queues allocated.
2803 : */
2804 19 : sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2805 19 : cq_allocated = (cpl->cdw0 >> 16) + 1;
2806 :
2807 : /*
2808 : * For 1:1 queue mapping, set number of allocated queues to be minimum of
2809 : * submission and completion queues.
2810 : */
2811 19 : min_allocated = spdk_min(sq_allocated, cq_allocated);
2812 :
2813 : /* Set number of queues to be minimum of requested and actually allocated. */
2814 19 : ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
2815 : }
2816 :
2817 19 : ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
2818 19 : if (ctrlr->free_io_qids == NULL) {
2819 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2820 0 : return;
2821 : }
2822 :
2823 : /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2824 69 : for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
2825 50 : spdk_nvme_ctrlr_free_qid(ctrlr, i);
2826 : }
2827 :
2828 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
2829 19 : ctrlr->opts.admin_timeout_ms);
2830 : }
2831 :
2832 : static int
2833 19 : nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2834 : {
2835 : int rc;
2836 :
2837 19 : if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
2838 0 : NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n",
2839 : ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2840 0 : ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
2841 19 : } else if (ctrlr->opts.num_io_queues < 1) {
2842 13 : NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n");
2843 13 : ctrlr->opts.num_io_queues = 1;
2844 : }
2845 :
2846 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2847 19 : ctrlr->opts.admin_timeout_ms);
2848 :
2849 19 : rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
2850 : nvme_ctrlr_set_num_queues_done, ctrlr);
2851 19 : if (rc != 0) {
2852 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2853 0 : return rc;
2854 : }
2855 :
2856 19 : return 0;
2857 : }
2858 :
2859 : static void
2860 3 : nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2861 : {
2862 : uint32_t keep_alive_interval_us;
2863 3 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2864 :
2865 3 : if (spdk_nvme_cpl_is_error(cpl)) {
2866 2 : if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
2867 2 : (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
2868 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n");
2869 : } else {
2870 1 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n",
2871 : cpl->status.sc, cpl->status.sct);
2872 1 : ctrlr->opts.keep_alive_timeout_ms = 0;
2873 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2874 1 : return;
2875 : }
2876 : } else {
2877 1 : if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
2878 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n",
2879 : cpl->cdw0);
2880 : }
2881 :
2882 1 : ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
2883 : }
2884 :
2885 2 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2886 0 : ctrlr->keep_alive_interval_ticks = 0;
2887 : } else {
2888 2 : keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
2889 :
2890 2 : NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us);
2891 :
2892 2 : ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
2893 : UINT64_C(1000000);
2894 :
2895 : /* Schedule the first Keep Alive to be sent as soon as possible. */
2896 2 : ctrlr->next_keep_alive_tick = spdk_get_ticks();
2897 : }
2898 :
2899 2 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2900 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2901 : } else {
2902 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2903 2 : ctrlr->opts.admin_timeout_ms);
2904 : }
2905 : }
2906 :
2907 : static int
2908 22 : nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
2909 : {
2910 : int rc;
2911 :
2912 22 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2913 19 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
2914 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2915 : } else {
2916 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2917 19 : ctrlr->opts.admin_timeout_ms);
2918 : }
2919 19 : return 0;
2920 : }
2921 :
2922 : /* Note: Discovery controller identify data does not populate KAS according to spec. */
2923 3 : if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) {
2924 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n");
2925 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
2926 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
2927 0 : ctrlr->opts.admin_timeout_ms);
2928 0 : return 0;
2929 : }
2930 :
2931 3 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
2932 3 : ctrlr->opts.admin_timeout_ms);
2933 :
2934 : /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
2935 3 : rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
2936 : nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
2937 3 : if (rc != 0) {
2938 0 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc);
2939 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
2940 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2941 0 : return rc;
2942 : }
2943 :
2944 3 : return 0;
2945 : }
2946 :
2947 : static void
2948 0 : nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
2949 : {
2950 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2951 :
2952 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2953 : /*
2954 : * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
2955 : * is optional.
2956 : */
2957 0 : NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
2958 : cpl->status.sc, cpl->status.sct);
2959 : } else {
2960 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n");
2961 : }
2962 :
2963 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2964 0 : }
2965 :
2966 : static int
2967 14 : nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
2968 : {
2969 : uint8_t *host_id;
2970 : uint32_t host_id_size;
2971 : int rc;
2972 :
2973 14 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
2974 : /*
2975 : * NVMe-oF sends the host ID during Connect and doesn't allow
2976 : * Set Features - Host Identifier after Connect, so we don't need to do anything here.
2977 : */
2978 14 : NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n");
2979 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2980 14 : return 0;
2981 : }
2982 :
2983 0 : if (ctrlr->cdata.ctratt.host_id_exhid_supported) {
2984 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n");
2985 0 : host_id = ctrlr->opts.extended_host_id;
2986 0 : host_id_size = sizeof(ctrlr->opts.extended_host_id);
2987 : } else {
2988 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n");
2989 0 : host_id = ctrlr->opts.host_id;
2990 0 : host_id_size = sizeof(ctrlr->opts.host_id);
2991 : }
2992 :
2993 : /* If the user specified an all-zeroes host identifier, don't send the command. */
2994 0 : if (spdk_mem_all_zero(host_id, host_id_size)) {
2995 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n");
2996 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
2997 0 : return 0;
2998 : }
2999 :
3000 0 : SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
3001 :
3002 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
3003 0 : ctrlr->opts.admin_timeout_ms);
3004 :
3005 0 : rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
3006 0 : if (rc != 0) {
3007 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc);
3008 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3009 0 : return rc;
3010 : }
3011 :
3012 0 : return 0;
3013 : }
3014 :
3015 : void
3016 4 : nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
3017 : {
3018 : uint32_t nsid;
3019 : struct spdk_nvme_ns *ns;
3020 :
3021 4 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
3022 19 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) {
3023 15 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
3024 15 : nvme_ns_construct(ns, nsid, ctrlr);
3025 : }
3026 4 : }
3027 :
3028 : static int
3029 4 : nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr)
3030 : {
3031 : struct nvme_completion_poll_status *status;
3032 4 : int rc = -ENOMEM;
3033 4 : char *buffer = NULL;
3034 : uint32_t nsid;
3035 4 : size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t));
3036 :
3037 4 : if (ctrlr->opts.disable_read_changed_ns_list_log_page) {
3038 0 : return 0;
3039 : }
3040 :
3041 4 : buffer = spdk_dma_zmalloc(buf_size, 4096, NULL);
3042 4 : if (!buffer) {
3043 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting "
3044 : "changed ns log.\n");
3045 0 : return rc;
3046 : }
3047 :
3048 4 : status = calloc(1, sizeof(*status));
3049 4 : if (!status) {
3050 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
3051 0 : goto free_buffer;
3052 : }
3053 :
3054 4 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr,
3055 : SPDK_NVME_LOG_CHANGED_NS_LIST,
3056 : SPDK_NVME_GLOBAL_NS_TAG,
3057 : buffer, buf_size, 0,
3058 : nvme_completion_poll_cb, status);
3059 :
3060 4 : if (rc) {
3061 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc);
3062 0 : free(status);
3063 0 : goto free_buffer;
3064 : }
3065 :
3066 4 : rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status,
3067 4 : ctrlr->opts.admin_timeout_ms * 1000);
3068 4 : if (!status->timed_out) {
3069 4 : free(status);
3070 : }
3071 :
3072 4 : if (rc) {
3073 0 : NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc);
3074 0 : goto free_buffer;
3075 : }
3076 :
3077 : /* only check the case of overflow. */
3078 4 : nsid = from_le32(buffer);
3079 4 : if (nsid == 0xffffffffu) {
3080 0 : NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n");
3081 : }
3082 :
3083 4 : free_buffer:
3084 4 : spdk_dma_free(buffer);
3085 4 : return rc;
3086 : }
3087 :
3088 : void
3089 5 : nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr,
3090 : const struct spdk_nvme_cpl *cpl)
3091 : {
3092 : union spdk_nvme_async_event_completion event;
3093 : struct spdk_nvme_ctrlr_process *active_proc;
3094 : int rc;
3095 :
3096 5 : event.raw = cpl->cdw0;
3097 :
3098 5 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3099 5 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
3100 4 : nvme_ctrlr_clear_changed_ns_log(ctrlr);
3101 :
3102 4 : rc = nvme_ctrlr_identify_active_ns(ctrlr);
3103 4 : if (rc) {
3104 0 : return;
3105 : }
3106 4 : nvme_ctrlr_update_namespaces(ctrlr);
3107 4 : nvme_io_msg_ctrlr_update(ctrlr);
3108 : }
3109 :
3110 5 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3111 5 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
3112 1 : if (!ctrlr->opts.disable_read_ana_log_page) {
3113 1 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
3114 1 : if (rc) {
3115 0 : return;
3116 : }
3117 1 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
3118 : ctrlr);
3119 : }
3120 : }
3121 :
3122 5 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3123 5 : if (active_proc && active_proc->aer_cb_fn) {
3124 3 : active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
3125 : }
3126 : }
3127 :
3128 : static void
3129 5 : nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr,
3130 : const struct spdk_nvme_cpl *cpl)
3131 : {
3132 : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event;
3133 : struct spdk_nvme_ctrlr_process *proc;
3134 :
3135 : /* Add async event to each process objects event list */
3136 10 : TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
3137 : /* Must be shared memory so other processes can access */
3138 5 : nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3139 5 : if (!nvme_event) {
3140 0 : NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n");
3141 0 : return;
3142 : }
3143 5 : nvme_event->cpl = *cpl;
3144 :
3145 5 : STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link);
3146 : }
3147 : }
3148 :
3149 : void
3150 5 : nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr)
3151 : {
3152 : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp;
3153 : struct spdk_nvme_ctrlr_process *active_proc;
3154 :
3155 5 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3156 :
3157 10 : STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) {
3158 5 : STAILQ_REMOVE(&active_proc->async_events, nvme_event,
3159 : spdk_nvme_ctrlr_aer_completion_list, link);
3160 5 : nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl);
3161 5 : spdk_free(nvme_event);
3162 :
3163 : }
3164 5 : }
3165 :
3166 : static void
3167 5 : nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
3168 : {
3169 5 : struct nvme_async_event_request *aer = arg;
3170 5 : struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
3171 :
3172 5 : if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
3173 5 : cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
3174 : /*
3175 : * This is simulated when controller is being shut down, to
3176 : * effectively abort outstanding asynchronous event requests
3177 : * and make sure all memory is freed. Do not repost the
3178 : * request in this case.
3179 : */
3180 0 : return;
3181 : }
3182 :
3183 5 : if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
3184 0 : cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
3185 : /*
3186 : * SPDK will only send as many AERs as the device says it supports,
3187 : * so this status code indicates an out-of-spec device. Do not repost
3188 : * the request in this case.
3189 : */
3190 0 : NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n"
3191 : "handling. Do not repost this AER.\n");
3192 0 : return;
3193 : }
3194 :
3195 : /* Add the events to the list */
3196 5 : nvme_ctrlr_queue_async_event(ctrlr, cpl);
3197 :
3198 : /* If the ctrlr was removed or in the destruct state, we should not send aer again */
3199 5 : if (ctrlr->is_removed || ctrlr->is_destructed) {
3200 0 : return;
3201 : }
3202 :
3203 : /*
3204 : * Repost another asynchronous event request to replace the one
3205 : * that just completed.
3206 : */
3207 5 : if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
3208 : /*
3209 : * We can't do anything to recover from a failure here,
3210 : * so just print a warning message and leave the AER unsubmitted.
3211 : */
3212 0 : NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n");
3213 : }
3214 : }
3215 :
3216 : static int
3217 24 : nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
3218 : struct nvme_async_event_request *aer)
3219 : {
3220 : struct nvme_request *req;
3221 :
3222 24 : aer->ctrlr = ctrlr;
3223 24 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
3224 24 : aer->req = req;
3225 24 : if (req == NULL) {
3226 0 : return -1;
3227 : }
3228 :
3229 24 : req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
3230 24 : return nvme_ctrlr_submit_admin_request(ctrlr, req);
3231 : }
3232 :
3233 : static void
3234 19 : nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
3235 : {
3236 : struct nvme_async_event_request *aer;
3237 : int rc;
3238 : uint32_t i;
3239 19 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3240 :
3241 19 : if (spdk_nvme_cpl_is_error(cpl)) {
3242 0 : NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n");
3243 0 : ctrlr->num_aers = 0;
3244 : } else {
3245 : /* aerl is a zero-based value, so we need to add 1 here. */
3246 19 : ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
3247 : }
3248 :
3249 38 : for (i = 0; i < ctrlr->num_aers; i++) {
3250 19 : aer = &ctrlr->aer[i];
3251 19 : rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
3252 19 : if (rc) {
3253 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
3254 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3255 0 : return;
3256 : }
3257 : }
3258 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms);
3259 : }
3260 :
3261 : static int
3262 19 : nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
3263 : {
3264 : union spdk_nvme_feat_async_event_configuration config;
3265 : int rc;
3266 :
3267 19 : config.raw = 0;
3268 :
3269 19 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3270 0 : config.bits.discovery_log_change_notice = 1;
3271 : } else {
3272 19 : config.bits.crit_warn.bits.available_spare = 1;
3273 19 : config.bits.crit_warn.bits.temperature = 1;
3274 19 : config.bits.crit_warn.bits.device_reliability = 1;
3275 19 : config.bits.crit_warn.bits.read_only = 1;
3276 19 : config.bits.crit_warn.bits.volatile_memory_backup = 1;
3277 :
3278 19 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
3279 4 : if (ctrlr->cdata.oaes.ns_attribute_notices) {
3280 0 : config.bits.ns_attr_notice = 1;
3281 : }
3282 4 : if (ctrlr->cdata.oaes.fw_activation_notices) {
3283 0 : config.bits.fw_activation_notice = 1;
3284 : }
3285 4 : if (ctrlr->cdata.oaes.ana_change_notices) {
3286 0 : config.bits.ana_change_notice = 1;
3287 : }
3288 : }
3289 19 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
3290 0 : config.bits.telemetry_log_notice = 1;
3291 : }
3292 : }
3293 :
3294 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
3295 19 : ctrlr->opts.admin_timeout_ms);
3296 :
3297 19 : rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
3298 : nvme_ctrlr_configure_aer_done,
3299 : ctrlr);
3300 19 : if (rc != 0) {
3301 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3302 0 : return rc;
3303 : }
3304 :
3305 19 : return 0;
3306 : }
3307 :
3308 : struct spdk_nvme_ctrlr_process *
3309 61 : nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
3310 : {
3311 : struct spdk_nvme_ctrlr_process *active_proc;
3312 :
3313 61 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3314 12 : if (active_proc->pid == pid) {
3315 12 : return active_proc;
3316 : }
3317 : }
3318 :
3319 49 : return NULL;
3320 : }
3321 :
3322 : struct spdk_nvme_ctrlr_process *
3323 57 : nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
3324 : {
3325 57 : return nvme_ctrlr_get_process(ctrlr, getpid());
3326 : }
3327 :
3328 : /**
3329 : * This function will be called when a process is using the controller.
3330 : * 1. For the primary process, it is called when constructing the controller.
3331 : * 2. For the secondary process, it is called at probing the controller.
3332 : * Note: will check whether the process is already added for the same process.
3333 : */
3334 : int
3335 4 : nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
3336 : {
3337 : struct spdk_nvme_ctrlr_process *ctrlr_proc;
3338 4 : pid_t pid = getpid();
3339 :
3340 : /* Check whether the process is already added or not */
3341 4 : if (nvme_ctrlr_get_process(ctrlr, pid)) {
3342 0 : return 0;
3343 : }
3344 :
3345 : /* Initialize the per process properties for this ctrlr */
3346 4 : ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
3347 : 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3348 4 : if (ctrlr_proc == NULL) {
3349 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n");
3350 :
3351 0 : return -1;
3352 : }
3353 :
3354 4 : ctrlr_proc->is_primary = spdk_process_is_primary();
3355 4 : ctrlr_proc->pid = pid;
3356 4 : STAILQ_INIT(&ctrlr_proc->active_reqs);
3357 4 : ctrlr_proc->devhandle = devhandle;
3358 4 : ctrlr_proc->ref = 0;
3359 4 : TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
3360 4 : STAILQ_INIT(&ctrlr_proc->async_events);
3361 :
3362 4 : TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
3363 :
3364 4 : return 0;
3365 : }
3366 :
3367 : /**
3368 : * This function will be called when the process detaches the controller.
3369 : * Note: the ctrlr_lock must be held when calling this function.
3370 : */
3371 : static void
3372 1 : nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
3373 : struct spdk_nvme_ctrlr_process *proc)
3374 : {
3375 : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3376 :
3377 1 : assert(STAILQ_EMPTY(&proc->active_reqs));
3378 :
3379 1 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3380 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3381 : }
3382 :
3383 1 : TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
3384 :
3385 1 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
3386 1 : spdk_pci_device_detach(proc->devhandle);
3387 : }
3388 :
3389 1 : spdk_free(proc);
3390 1 : }
3391 :
3392 : /**
3393 : * This function will be called when the process exited unexpectedly
3394 : * in order to free any incomplete nvme request, allocated IO qpairs
3395 : * and allocated memory.
3396 : * Note: the ctrlr_lock must be held when calling this function.
3397 : */
3398 : static void
3399 0 : nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
3400 : {
3401 : struct nvme_request *req, *tmp_req;
3402 : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3403 : struct spdk_nvme_ctrlr_aer_completion_list *event;
3404 :
3405 0 : STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
3406 0 : STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
3407 :
3408 0 : assert(req->pid == proc->pid);
3409 0 : nvme_cleanup_user_req(req);
3410 0 : nvme_free_request(req);
3411 : }
3412 :
3413 : /* Remove async event from each process objects event list */
3414 0 : while (!STAILQ_EMPTY(&proc->async_events)) {
3415 0 : event = STAILQ_FIRST(&proc->async_events);
3416 0 : STAILQ_REMOVE_HEAD(&proc->async_events, link);
3417 0 : spdk_free(event);
3418 : }
3419 :
3420 0 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3421 0 : TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
3422 :
3423 : /*
3424 : * The process may have been killed while some qpairs were in their
3425 : * completion context. Clear that flag here to allow these IO
3426 : * qpairs to be deleted.
3427 : */
3428 0 : qpair->in_completion_context = 0;
3429 :
3430 0 : qpair->no_deletion_notification_needed = 1;
3431 :
3432 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3433 : }
3434 :
3435 0 : spdk_free(proc);
3436 0 : }
3437 :
3438 : /**
3439 : * This function will be called when destructing the controller.
3440 : * 1. There is no more admin request on this controller.
3441 : * 2. Clean up any left resource allocation when its associated process is gone.
3442 : */
3443 : void
3444 49 : nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
3445 : {
3446 : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3447 :
3448 : /* Free all the processes' properties and make sure no pending admin IOs */
3449 52 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3450 3 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3451 :
3452 3 : assert(STAILQ_EMPTY(&active_proc->active_reqs));
3453 :
3454 3 : spdk_free(active_proc);
3455 : }
3456 49 : }
3457 :
3458 : /**
3459 : * This function will be called when any other process attaches or
3460 : * detaches the controller in order to cleanup those unexpectedly
3461 : * terminated processes.
3462 : * Note: the ctrlr_lock must be held when calling this function.
3463 : */
3464 : static int
3465 0 : nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
3466 : {
3467 : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3468 0 : int active_proc_count = 0;
3469 :
3470 0 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3471 0 : if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
3472 0 : NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid);
3473 :
3474 0 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3475 :
3476 0 : nvme_ctrlr_cleanup_process(active_proc);
3477 : } else {
3478 0 : active_proc_count++;
3479 : }
3480 : }
3481 :
3482 0 : return active_proc_count;
3483 : }
3484 :
3485 : void
3486 0 : nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
3487 : {
3488 : struct spdk_nvme_ctrlr_process *active_proc;
3489 :
3490 0 : nvme_ctrlr_lock(ctrlr);
3491 :
3492 0 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3493 :
3494 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3495 0 : if (active_proc) {
3496 0 : active_proc->ref++;
3497 : }
3498 :
3499 0 : nvme_ctrlr_unlock(ctrlr);
3500 0 : }
3501 :
3502 : void
3503 0 : nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
3504 : {
3505 : struct spdk_nvme_ctrlr_process *active_proc;
3506 : int proc_count;
3507 :
3508 0 : nvme_ctrlr_lock(ctrlr);
3509 :
3510 0 : proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
3511 :
3512 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3513 0 : if (active_proc) {
3514 0 : active_proc->ref--;
3515 0 : assert(active_proc->ref >= 0);
3516 :
3517 : /*
3518 : * The last active process will be removed at the end of
3519 : * the destruction of the controller.
3520 : */
3521 0 : if (active_proc->ref == 0 && proc_count != 1) {
3522 0 : nvme_ctrlr_remove_process(ctrlr, active_proc);
3523 : }
3524 : }
3525 :
3526 0 : nvme_ctrlr_unlock(ctrlr);
3527 0 : }
3528 :
3529 : int
3530 0 : nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
3531 : {
3532 : struct spdk_nvme_ctrlr_process *active_proc;
3533 0 : int ref = 0;
3534 :
3535 0 : nvme_ctrlr_lock(ctrlr);
3536 :
3537 0 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3538 :
3539 0 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3540 0 : ref += active_proc->ref;
3541 : }
3542 :
3543 0 : nvme_ctrlr_unlock(ctrlr);
3544 :
3545 0 : return ref;
3546 : }
3547 :
3548 : /**
3549 : * Get the PCI device handle which is only visible to its associated process.
3550 : */
3551 : struct spdk_pci_device *
3552 0 : nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
3553 : {
3554 : struct spdk_nvme_ctrlr_process *active_proc;
3555 0 : struct spdk_pci_device *devhandle = NULL;
3556 :
3557 0 : nvme_ctrlr_lock(ctrlr);
3558 :
3559 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3560 0 : if (active_proc) {
3561 0 : devhandle = active_proc->devhandle;
3562 : }
3563 :
3564 0 : nvme_ctrlr_unlock(ctrlr);
3565 :
3566 0 : return devhandle;
3567 : }
3568 :
3569 : static void
3570 21 : nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3571 : {
3572 21 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3573 :
3574 21 : if (spdk_nvme_cpl_is_error(cpl)) {
3575 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n");
3576 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3577 0 : return;
3578 : }
3579 :
3580 21 : assert(value <= UINT32_MAX);
3581 21 : ctrlr->vs.raw = (uint32_t)value;
3582 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
3583 : }
3584 :
3585 : static void
3586 21 : nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3587 : {
3588 21 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3589 :
3590 21 : if (spdk_nvme_cpl_is_error(cpl)) {
3591 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
3592 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3593 0 : return;
3594 : }
3595 :
3596 21 : ctrlr->cap.raw = value;
3597 21 : nvme_ctrlr_init_cap(ctrlr);
3598 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
3599 : }
3600 :
3601 : static void
3602 22 : nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3603 : {
3604 22 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3605 : enum nvme_ctrlr_state state;
3606 :
3607 22 : if (spdk_nvme_cpl_is_error(cpl)) {
3608 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3609 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3610 0 : return;
3611 : }
3612 :
3613 22 : assert(value <= UINT32_MAX);
3614 22 : ctrlr->process_init_cc.raw = (uint32_t)value;
3615 :
3616 22 : if (ctrlr->process_init_cc.bits.en) {
3617 2 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n");
3618 2 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1;
3619 : } else {
3620 20 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0;
3621 : }
3622 :
3623 22 : nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr));
3624 : }
3625 :
3626 : static void
3627 2 : nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3628 : {
3629 2 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3630 :
3631 2 : if (spdk_nvme_cpl_is_error(cpl)) {
3632 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n");
3633 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3634 0 : return;
3635 : }
3636 :
3637 : /*
3638 : * Wait 2.5 seconds before accessing PCI registers.
3639 : * Not using sleep() to avoid blocking other controller's initialization.
3640 : */
3641 2 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
3642 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n");
3643 0 : ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000);
3644 : }
3645 :
3646 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3647 : nvme_ctrlr_get_ready_timeout(ctrlr));
3648 : }
3649 :
3650 : static void
3651 2 : nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3652 : {
3653 2 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3654 : union spdk_nvme_cc_register cc;
3655 : int rc;
3656 :
3657 2 : if (spdk_nvme_cpl_is_error(cpl)) {
3658 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3659 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3660 0 : return;
3661 : }
3662 :
3663 2 : assert(value <= UINT32_MAX);
3664 2 : cc.raw = (uint32_t)value;
3665 2 : cc.bits.en = 0;
3666 2 : ctrlr->process_init_cc.raw = cc.raw;
3667 :
3668 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC,
3669 : nvme_ctrlr_get_ready_timeout(ctrlr));
3670 :
3671 2 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr);
3672 2 : if (rc != 0) {
3673 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
3674 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3675 : }
3676 : }
3677 :
3678 : static void
3679 2 : nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3680 : {
3681 2 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3682 : union spdk_nvme_csts_register csts;
3683 :
3684 2 : if (spdk_nvme_cpl_is_error(cpl)) {
3685 : /* While a device is resetting, it may be unable to service MMIO reads
3686 : * temporarily. Allow for this case.
3687 : */
3688 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3689 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
3690 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3691 : NVME_TIMEOUT_KEEP_EXISTING);
3692 : } else {
3693 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3694 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3695 : }
3696 :
3697 0 : return;
3698 : }
3699 :
3700 2 : assert(value <= UINT32_MAX);
3701 2 : csts.raw = (uint32_t)value;
3702 2 : if (csts.bits.rdy == 1 || csts.bits.cfs == 1) {
3703 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0,
3704 : nvme_ctrlr_get_ready_timeout(ctrlr));
3705 : } else {
3706 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
3707 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3708 : NVME_TIMEOUT_KEEP_EXISTING);
3709 : }
3710 : }
3711 :
3712 : static void
3713 22 : nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3714 : {
3715 22 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3716 : union spdk_nvme_csts_register csts;
3717 :
3718 22 : if (spdk_nvme_cpl_is_error(cpl)) {
3719 : /* While a device is resetting, it may be unable to service MMIO reads
3720 : * temporarily. Allow for this case.
3721 : */
3722 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3723 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
3724 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3725 : NVME_TIMEOUT_KEEP_EXISTING);
3726 : } else {
3727 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3728 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3729 : }
3730 :
3731 0 : return;
3732 : }
3733 :
3734 22 : assert(value <= UINT32_MAX);
3735 22 : csts.raw = (uint32_t)value;
3736 22 : if (csts.bits.rdy == 0) {
3737 22 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n");
3738 22 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED,
3739 : nvme_ctrlr_get_ready_timeout(ctrlr));
3740 : } else {
3741 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3742 : NVME_TIMEOUT_KEEP_EXISTING);
3743 : }
3744 : }
3745 :
3746 : static void
3747 9 : nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
3748 : const struct spdk_nvme_cpl *cpl)
3749 : {
3750 9 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3751 : union spdk_nvme_csts_register csts;
3752 :
3753 9 : if (spdk_nvme_cpl_is_error(cpl)) {
3754 : /* While a device is resetting, it may be unable to service MMIO reads
3755 : * temporarily. Allow for this case.
3756 : */
3757 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3758 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
3759 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3760 : NVME_TIMEOUT_KEEP_EXISTING);
3761 : } else {
3762 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3763 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3764 : }
3765 :
3766 0 : return;
3767 : }
3768 :
3769 9 : assert(value <= UINT32_MAX);
3770 9 : csts.raw = value;
3771 9 : if (csts.bits.rdy == 1) {
3772 9 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
3773 : /*
3774 : * The controller has been enabled.
3775 : * Perform the rest of initialization serially.
3776 : */
3777 9 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3778 9 : ctrlr->opts.admin_timeout_ms);
3779 : } else {
3780 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3781 : NVME_TIMEOUT_KEEP_EXISTING);
3782 : }
3783 : }
3784 :
3785 : /**
3786 : * This function will be called repeatedly during initialization until the controller is ready.
3787 : */
3788 : int
3789 430 : nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
3790 : {
3791 : uint32_t ready_timeout_in_ms;
3792 : uint64_t ticks;
3793 430 : int rc = 0;
3794 :
3795 430 : ticks = spdk_get_ticks();
3796 :
3797 : /*
3798 : * May need to avoid accessing any register on the target controller
3799 : * for a while. Return early without touching the FSM.
3800 : * Check sleep_timeout_tsc > 0 for unit test.
3801 : */
3802 430 : if ((ctrlr->sleep_timeout_tsc > 0) &&
3803 2 : (ticks <= ctrlr->sleep_timeout_tsc)) {
3804 1 : return 0;
3805 : }
3806 429 : ctrlr->sleep_timeout_tsc = 0;
3807 :
3808 429 : ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr);
3809 :
3810 : /*
3811 : * Check if the current initialization step is done or has timed out.
3812 : */
3813 429 : switch (ctrlr->state) {
3814 1 : case NVME_CTRLR_STATE_INIT_DELAY:
3815 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3816 1 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
3817 : /*
3818 : * Controller may need some delay before it's enabled.
3819 : *
3820 : * This is a workaround for an issue where the PCIe-attached NVMe controller
3821 : * is not ready after VFIO reset. We delay the initialization rather than the
3822 : * enabling itself, because this is required only for the very first enabling
3823 : * - directly after a VFIO reset.
3824 : */
3825 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n");
3826 1 : ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
3827 : }
3828 1 : break;
3829 :
3830 0 : case NVME_CTRLR_STATE_DISCONNECTED:
3831 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3832 0 : break;
3833 :
3834 21 : case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */
3835 21 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
3836 21 : if (rc == 0) {
3837 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ,
3838 : NVME_TIMEOUT_INFINITE);
3839 : } else {
3840 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3841 : }
3842 21 : break;
3843 :
3844 21 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
3845 21 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3846 :
3847 21 : switch (nvme_qpair_get_state(ctrlr->adminq)) {
3848 0 : case NVME_QPAIR_CONNECTING:
3849 0 : break;
3850 21 : case NVME_QPAIR_CONNECTED:
3851 21 : nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
3852 : /* Fall through */
3853 21 : case NVME_QPAIR_ENABLED:
3854 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS,
3855 : NVME_TIMEOUT_INFINITE);
3856 : /* Abort any queued requests that were sent while the adminq was connecting
3857 : * to avoid stalling the init process during a reset, as requests don't get
3858 : * resubmitted while the controller is resetting and subsequent commands
3859 : * would get queued too.
3860 : */
3861 21 : nvme_qpair_abort_queued_reqs(ctrlr->adminq);
3862 21 : break;
3863 0 : case NVME_QPAIR_DISCONNECTING:
3864 0 : assert(ctrlr->adminq->async == true);
3865 0 : break;
3866 0 : case NVME_QPAIR_DISCONNECTED:
3867 : /* fallthrough */
3868 : default:
3869 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3870 0 : break;
3871 : }
3872 :
3873 21 : break;
3874 :
3875 21 : case NVME_CTRLR_STATE_READ_VS:
3876 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE);
3877 21 : rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr);
3878 21 : break;
3879 :
3880 21 : case NVME_CTRLR_STATE_READ_CAP:
3881 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
3882 21 : rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
3883 21 : break;
3884 :
3885 22 : case NVME_CTRLR_STATE_CHECK_EN:
3886 : /* Begin the hardware initialization by making sure the controller is disabled. */
3887 22 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms);
3888 22 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr);
3889 22 : break;
3890 :
3891 2 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
3892 : /*
3893 : * Controller is currently enabled. We need to disable it to cause a reset.
3894 : *
3895 : * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
3896 : * Wait for the ready bit to be 1 before disabling the controller.
3897 : */
3898 2 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3899 : NVME_TIMEOUT_KEEP_EXISTING);
3900 2 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
3901 2 : break;
3902 :
3903 2 : case NVME_CTRLR_STATE_SET_EN_0:
3904 2 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n");
3905 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms);
3906 2 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr);
3907 2 : break;
3908 :
3909 22 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
3910 22 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
3911 : NVME_TIMEOUT_KEEP_EXISTING);
3912 22 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
3913 22 : break;
3914 :
3915 21 : case NVME_CTRLR_STATE_DISABLED:
3916 21 : if (ctrlr->is_disconnecting) {
3917 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n");
3918 : } else {
3919 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
3920 :
3921 : /*
3922 : * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
3923 : * set to 1 if it is too soon after CSTS.RDY is reported as 0.
3924 : */
3925 21 : spdk_delay_us(100);
3926 : }
3927 21 : break;
3928 :
3929 21 : case NVME_CTRLR_STATE_ENABLE:
3930 21 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n");
3931 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms);
3932 21 : rc = nvme_ctrlr_enable(ctrlr);
3933 21 : if (rc) {
3934 7 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc);
3935 : }
3936 21 : return rc;
3937 :
3938 9 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
3939 9 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
3940 : NVME_TIMEOUT_KEEP_EXISTING);
3941 9 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
3942 : ctrlr);
3943 9 : break;
3944 :
3945 9 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
3946 9 : nvme_transport_qpair_reset(ctrlr->adminq);
3947 9 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
3948 9 : break;
3949 :
3950 16 : case NVME_CTRLR_STATE_IDENTIFY:
3951 16 : rc = nvme_ctrlr_identify(ctrlr);
3952 16 : break;
3953 :
3954 19 : case NVME_CTRLR_STATE_CONFIGURE_AER:
3955 19 : rc = nvme_ctrlr_configure_aer(ctrlr);
3956 19 : break;
3957 :
3958 22 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
3959 22 : rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
3960 22 : break;
3961 :
3962 19 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
3963 19 : rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
3964 19 : break;
3965 :
3966 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
3967 0 : rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
3968 0 : break;
3969 :
3970 19 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
3971 19 : nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
3972 19 : rc = nvme_ctrlr_set_num_queues(ctrlr);
3973 19 : break;
3974 :
3975 24 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
3976 24 : _nvme_ctrlr_identify_active_ns(ctrlr);
3977 24 : break;
3978 :
3979 14 : case NVME_CTRLR_STATE_IDENTIFY_NS:
3980 14 : rc = nvme_ctrlr_identify_namespaces(ctrlr);
3981 14 : break;
3982 :
3983 14 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
3984 14 : rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
3985 14 : break;
3986 :
3987 14 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
3988 14 : rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
3989 14 : break;
3990 :
3991 15 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
3992 15 : rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
3993 15 : break;
3994 :
3995 1 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
3996 1 : rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
3997 1 : break;
3998 :
3999 14 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
4000 14 : nvme_ctrlr_set_supported_features(ctrlr);
4001 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
4002 14 : ctrlr->opts.admin_timeout_ms);
4003 14 : break;
4004 :
4005 14 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
4006 14 : rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
4007 14 : break;
4008 :
4009 14 : case NVME_CTRLR_STATE_SET_HOST_ID:
4010 14 : rc = nvme_ctrlr_set_host_id(ctrlr);
4011 14 : break;
4012 :
4013 17 : case NVME_CTRLR_STATE_TRANSPORT_READY:
4014 17 : rc = nvme_transport_ctrlr_ready(ctrlr);
4015 17 : if (rc) {
4016 1 : NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc);
4017 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4018 : } else {
4019 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
4020 : }
4021 17 : break;
4022 :
4023 0 : case NVME_CTRLR_STATE_READY:
4024 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n");
4025 0 : return 0;
4026 :
4027 0 : case NVME_CTRLR_STATE_ERROR:
4028 0 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n");
4029 0 : return -1;
4030 :
4031 0 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
4032 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
4033 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
4034 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
4035 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4036 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
4037 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
4038 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4039 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
4040 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
4041 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
4042 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
4043 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
4044 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
4045 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
4046 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
4047 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
4048 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
4049 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
4050 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
4051 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
4052 : /*
4053 : * nvme_ctrlr_process_init() may be called from the completion context
4054 : * for the admin qpair. Avoid recursive calls for this case.
4055 : */
4056 0 : if (!ctrlr->adminq->in_completion_context) {
4057 0 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4058 : }
4059 0 : break;
4060 :
4061 0 : default:
4062 0 : assert(0);
4063 : return -1;
4064 : }
4065 :
4066 408 : if (rc) {
4067 1 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n",
4068 : rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4069 : }
4070 :
4071 : /* Note: we use the ticks captured when we entered this function.
4072 : * This covers environments where the SPDK process gets swapped out after
4073 : * we tried to advance the state but before we check the timeout here.
4074 : * It is not normal for this to happen, but harmless to handle it in this
4075 : * way.
4076 : */
4077 408 : if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
4078 0 : ticks > ctrlr->state_timeout_tsc) {
4079 0 : NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n",
4080 : ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4081 0 : return -1;
4082 : }
4083 :
4084 408 : return rc;
4085 : }
4086 :
4087 : int
4088 46 : nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
4089 : {
4090 46 : pthread_mutexattr_t attr;
4091 46 : int rc = 0;
4092 :
4093 46 : if (pthread_mutexattr_init(&attr)) {
4094 0 : return -1;
4095 : }
4096 92 : if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
4097 : #ifndef __FreeBSD__
4098 92 : pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
4099 92 : pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
4100 : #endif
4101 46 : pthread_mutex_init(mtx, &attr)) {
4102 0 : rc = -1;
4103 : }
4104 46 : pthread_mutexattr_destroy(&attr);
4105 46 : return rc;
4106 : }
4107 :
4108 : int
4109 46 : nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
4110 : {
4111 : int rc;
4112 :
4113 46 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
4114 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
4115 : } else {
4116 45 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
4117 : }
4118 :
4119 46 : if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
4120 0 : NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
4121 : ctrlr->opts.admin_queue_size);
4122 0 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
4123 : }
4124 :
4125 46 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE &&
4126 0 : (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) {
4127 0 : NVME_CTRLR_ERRLOG(ctrlr,
4128 : "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n",
4129 : ctrlr->opts.admin_queue_size);
4130 0 : ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size,
4131 : SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE);
4132 : }
4133 :
4134 46 : if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
4135 25 : NVME_CTRLR_ERRLOG(ctrlr,
4136 : "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
4137 : ctrlr->opts.admin_queue_size);
4138 25 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
4139 : }
4140 :
4141 46 : ctrlr->flags = 0;
4142 46 : ctrlr->free_io_qids = NULL;
4143 46 : ctrlr->is_resetting = false;
4144 46 : ctrlr->is_failed = false;
4145 46 : ctrlr->is_destructed = false;
4146 :
4147 46 : TAILQ_INIT(&ctrlr->active_io_qpairs);
4148 46 : STAILQ_INIT(&ctrlr->queued_aborts);
4149 46 : ctrlr->outstanding_aborts = 0;
4150 :
4151 46 : ctrlr->ana_log_page = NULL;
4152 46 : ctrlr->ana_log_page_size = 0;
4153 :
4154 46 : rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
4155 46 : if (rc != 0) {
4156 0 : return rc;
4157 : }
4158 :
4159 46 : TAILQ_INIT(&ctrlr->active_procs);
4160 46 : STAILQ_INIT(&ctrlr->register_operations);
4161 :
4162 46 : RB_INIT(&ctrlr->ns);
4163 :
4164 46 : return rc;
4165 : }
4166 :
4167 : static void
4168 21 : nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
4169 : {
4170 21 : if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
4171 5 : ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
4172 : }
4173 :
4174 21 : ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
4175 :
4176 : /* For now, always select page_size == min_page_size. */
4177 21 : ctrlr->page_size = ctrlr->min_page_size;
4178 :
4179 21 : ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
4180 21 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
4181 21 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE &&
4182 0 : ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) {
4183 : /* If the user specifically set an IO queue size different than the
4184 : * default, use that value. Otherwise overwrite with the quirked value.
4185 : * This allows this quirk to be overridden when necessary.
4186 : * However, cap.mqes still needs to be respected.
4187 : */
4188 0 : ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK;
4189 : }
4190 21 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
4191 :
4192 21 : ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
4193 21 : }
4194 :
4195 : void
4196 46 : nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
4197 : {
4198 : int rc;
4199 :
4200 46 : if (ctrlr->lock_depth > 0) {
4201 0 : SPDK_ERRLOG("lock currently held (depth=%d)!\n", ctrlr->lock_depth);
4202 0 : assert(false);
4203 : }
4204 :
4205 46 : rc = pthread_mutex_destroy(&ctrlr->ctrlr_lock);
4206 46 : if (rc) {
4207 0 : SPDK_ERRLOG("could not destroy ctrlr_lock: %s\n", spdk_strerror(rc));
4208 0 : assert(false);
4209 : }
4210 :
4211 46 : nvme_ctrlr_free_processes(ctrlr);
4212 46 : }
4213 :
4214 : void
4215 46 : nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
4216 : struct nvme_ctrlr_detach_ctx *ctx)
4217 : {
4218 : struct spdk_nvme_qpair *qpair, *tmp;
4219 :
4220 46 : NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n");
4221 :
4222 46 : ctrlr->prepare_for_reset = false;
4223 46 : ctrlr->is_destructed = true;
4224 :
4225 46 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4226 :
4227 46 : nvme_ctrlr_abort_queued_aborts(ctrlr);
4228 46 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
4229 :
4230 46 : TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
4231 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
4232 : }
4233 :
4234 46 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
4235 46 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
4236 :
4237 46 : nvme_ctrlr_shutdown_async(ctrlr, ctx);
4238 46 : }
4239 :
4240 : int
4241 84 : nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
4242 : struct nvme_ctrlr_detach_ctx *ctx)
4243 : {
4244 : struct spdk_nvme_ns *ns, *tmp_ns;
4245 84 : int rc = 0;
4246 :
4247 84 : if (!ctx->shutdown_complete) {
4248 76 : rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
4249 76 : if (rc == -EAGAIN) {
4250 38 : return -EAGAIN;
4251 : }
4252 : /* Destruct ctrlr forcefully for any other error. */
4253 : }
4254 :
4255 46 : if (ctx->cb_fn) {
4256 0 : ctx->cb_fn(ctrlr);
4257 : }
4258 :
4259 46 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
4260 :
4261 7732 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
4262 7686 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
4263 7686 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
4264 7686 : spdk_free(ns);
4265 : }
4266 :
4267 46 : ctrlr->active_ns_count = 0;
4268 :
4269 46 : spdk_bit_array_free(&ctrlr->free_io_qids);
4270 :
4271 46 : free(ctrlr->ana_log_page);
4272 46 : free(ctrlr->copied_ana_desc);
4273 46 : ctrlr->ana_log_page = NULL;
4274 46 : ctrlr->copied_ana_desc = NULL;
4275 46 : ctrlr->ana_log_page_size = 0;
4276 :
4277 46 : nvme_transport_ctrlr_destruct(ctrlr);
4278 :
4279 46 : return rc;
4280 : }
4281 :
4282 : void
4283 46 : nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
4284 : {
4285 46 : struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr };
4286 : int rc;
4287 :
4288 46 : nvme_ctrlr_destruct_async(ctrlr, &ctx);
4289 :
4290 : while (1) {
4291 84 : rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
4292 84 : if (rc != -EAGAIN) {
4293 46 : break;
4294 : }
4295 38 : nvme_delay(1000);
4296 : }
4297 46 : }
4298 :
4299 : int
4300 24 : nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
4301 : struct nvme_request *req)
4302 : {
4303 24 : return nvme_qpair_submit_request(ctrlr->adminq, req);
4304 : }
4305 :
4306 : static void
4307 0 : nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
4308 : {
4309 : /* Do nothing */
4310 0 : }
4311 :
4312 : /*
4313 : * Check if we need to send a Keep Alive command.
4314 : * Caller must hold ctrlr->ctrlr_lock.
4315 : */
4316 : static int
4317 0 : nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
4318 : {
4319 : uint64_t now;
4320 : struct nvme_request *req;
4321 : struct spdk_nvme_cmd *cmd;
4322 0 : int rc = 0;
4323 :
4324 0 : now = spdk_get_ticks();
4325 0 : if (now < ctrlr->next_keep_alive_tick) {
4326 0 : return rc;
4327 : }
4328 :
4329 0 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
4330 0 : if (req == NULL) {
4331 0 : return rc;
4332 : }
4333 :
4334 0 : cmd = &req->cmd;
4335 0 : cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
4336 :
4337 0 : rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
4338 0 : if (rc != 0) {
4339 0 : NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n");
4340 0 : rc = -ENXIO;
4341 : }
4342 :
4343 0 : ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
4344 0 : return rc;
4345 : }
4346 :
4347 : int32_t
4348 1 : spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
4349 : {
4350 : int32_t num_completions;
4351 : int32_t rc;
4352 : struct spdk_nvme_ctrlr_process *active_proc;
4353 :
4354 1 : nvme_ctrlr_lock(ctrlr);
4355 :
4356 1 : if (ctrlr->keep_alive_interval_ticks) {
4357 0 : rc = nvme_ctrlr_keep_alive(ctrlr);
4358 0 : if (rc) {
4359 0 : nvme_ctrlr_unlock(ctrlr);
4360 0 : return rc;
4361 : }
4362 : }
4363 :
4364 1 : rc = nvme_io_msg_process(ctrlr);
4365 1 : if (rc < 0) {
4366 0 : nvme_ctrlr_unlock(ctrlr);
4367 0 : return rc;
4368 : }
4369 1 : num_completions = rc;
4370 :
4371 1 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4372 :
4373 : /* Each process has an async list, complete the ones for this process object */
4374 1 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4375 1 : if (active_proc) {
4376 0 : nvme_ctrlr_complete_queued_async_events(ctrlr);
4377 : }
4378 :
4379 1 : if (rc == -ENXIO && ctrlr->is_disconnecting) {
4380 1 : nvme_ctrlr_disconnect_done(ctrlr);
4381 : }
4382 :
4383 1 : nvme_ctrlr_unlock(ctrlr);
4384 :
4385 1 : if (rc < 0) {
4386 1 : num_completions = rc;
4387 : } else {
4388 0 : num_completions += rc;
4389 : }
4390 :
4391 1 : return num_completions;
4392 : }
4393 :
4394 : const struct spdk_nvme_ctrlr_data *
4395 0 : spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
4396 : {
4397 0 : return &ctrlr->cdata;
4398 : }
4399 :
4400 0 : union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
4401 : {
4402 0 : union spdk_nvme_csts_register csts;
4403 :
4404 0 : if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
4405 0 : csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4406 : }
4407 0 : return csts;
4408 : }
4409 :
4410 0 : union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr)
4411 : {
4412 0 : union spdk_nvme_cc_register cc;
4413 :
4414 0 : if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
4415 0 : cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4416 : }
4417 0 : return cc;
4418 : }
4419 :
4420 0 : union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
4421 : {
4422 0 : return ctrlr->cap;
4423 : }
4424 :
4425 0 : union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
4426 : {
4427 0 : return ctrlr->vs;
4428 : }
4429 :
4430 0 : union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
4431 : {
4432 0 : union spdk_nvme_cmbsz_register cmbsz;
4433 :
4434 0 : if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
4435 0 : cmbsz.raw = 0;
4436 : }
4437 :
4438 0 : return cmbsz;
4439 : }
4440 :
4441 0 : union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
4442 : {
4443 0 : union spdk_nvme_pmrcap_register pmrcap;
4444 :
4445 0 : if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
4446 0 : pmrcap.raw = 0;
4447 : }
4448 :
4449 0 : return pmrcap;
4450 : }
4451 :
4452 0 : union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr)
4453 : {
4454 0 : union spdk_nvme_bpinfo_register bpinfo;
4455 :
4456 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
4457 0 : bpinfo.raw = 0;
4458 : }
4459 :
4460 0 : return bpinfo;
4461 : }
4462 :
4463 : uint64_t
4464 0 : spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr)
4465 : {
4466 0 : return ctrlr->pmr_size;
4467 : }
4468 :
4469 : uint32_t
4470 2 : spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
4471 : {
4472 2 : return ctrlr->cdata.nn;
4473 : }
4474 :
4475 : bool
4476 9301 : spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4477 : {
4478 9301 : struct spdk_nvme_ns tmp, *ns;
4479 :
4480 9301 : tmp.id = nsid;
4481 9301 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4482 :
4483 9301 : if (ns != NULL) {
4484 9209 : return ns->active;
4485 : }
4486 :
4487 92 : return false;
4488 : }
4489 :
4490 : uint32_t
4491 35 : spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
4492 : {
4493 : struct spdk_nvme_ns *ns;
4494 :
4495 35 : ns = RB_MIN(nvme_ns_tree, &ctrlr->ns);
4496 35 : if (ns == NULL) {
4497 10 : return 0;
4498 : }
4499 :
4500 4618 : while (ns != NULL) {
4501 4615 : if (ns->active) {
4502 22 : return ns->id;
4503 : }
4504 :
4505 4593 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4506 : }
4507 :
4508 3 : return 0;
4509 : }
4510 :
4511 : uint32_t
4512 4657 : spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
4513 : {
4514 4657 : struct spdk_nvme_ns tmp, *ns;
4515 :
4516 4657 : tmp.id = prev_nsid;
4517 4657 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4518 4657 : if (ns == NULL) {
4519 5 : return 0;
4520 : }
4521 :
4522 4652 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4523 6184 : while (ns != NULL) {
4524 6164 : if (ns->active) {
4525 4632 : return ns->id;
4526 : }
4527 :
4528 1532 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4529 : }
4530 :
4531 20 : return 0;
4532 : }
4533 :
4534 : struct spdk_nvme_ns *
4535 12403 : spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4536 : {
4537 12403 : struct spdk_nvme_ns tmp;
4538 : struct spdk_nvme_ns *ns;
4539 :
4540 12403 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
4541 18 : return NULL;
4542 : }
4543 :
4544 12385 : nvme_ctrlr_lock(ctrlr);
4545 :
4546 12385 : tmp.id = nsid;
4547 12385 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4548 :
4549 12385 : if (ns == NULL) {
4550 7687 : ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
4551 7687 : if (ns == NULL) {
4552 0 : nvme_ctrlr_unlock(ctrlr);
4553 0 : return NULL;
4554 : }
4555 :
4556 7687 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid);
4557 7687 : ns->id = nsid;
4558 7687 : RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns);
4559 : }
4560 :
4561 12385 : nvme_ctrlr_unlock(ctrlr);
4562 :
4563 12385 : return ns;
4564 : }
4565 :
4566 : struct spdk_pci_device *
4567 0 : spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
4568 : {
4569 0 : if (ctrlr == NULL) {
4570 0 : return NULL;
4571 : }
4572 :
4573 0 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
4574 0 : return NULL;
4575 : }
4576 :
4577 0 : return nvme_ctrlr_proc_get_devhandle(ctrlr);
4578 : }
4579 :
4580 : uint32_t
4581 0 : spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
4582 : {
4583 0 : return ctrlr->max_xfer_size;
4584 : }
4585 :
4586 : void
4587 2 : spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
4588 : spdk_nvme_aer_cb aer_cb_fn,
4589 : void *aer_cb_arg)
4590 : {
4591 : struct spdk_nvme_ctrlr_process *active_proc;
4592 :
4593 2 : nvme_ctrlr_lock(ctrlr);
4594 :
4595 2 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4596 2 : if (active_proc) {
4597 2 : active_proc->aer_cb_fn = aer_cb_fn;
4598 2 : active_proc->aer_cb_arg = aer_cb_arg;
4599 : }
4600 :
4601 2 : nvme_ctrlr_unlock(ctrlr);
4602 2 : }
4603 :
4604 : void
4605 0 : spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr)
4606 : {
4607 0 : ctrlr->opts.disable_read_changed_ns_list_log_page = true;
4608 0 : }
4609 :
4610 : void
4611 0 : spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
4612 : uint64_t timeout_io_us, uint64_t timeout_admin_us,
4613 : spdk_nvme_timeout_cb cb_fn, void *cb_arg)
4614 : {
4615 : struct spdk_nvme_ctrlr_process *active_proc;
4616 :
4617 0 : nvme_ctrlr_lock(ctrlr);
4618 :
4619 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4620 0 : if (active_proc) {
4621 0 : active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL;
4622 0 : active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL;
4623 0 : active_proc->timeout_cb_fn = cb_fn;
4624 0 : active_proc->timeout_cb_arg = cb_arg;
4625 : }
4626 :
4627 0 : ctrlr->timeout_enabled = true;
4628 :
4629 0 : nvme_ctrlr_unlock(ctrlr);
4630 0 : }
4631 :
4632 : bool
4633 8 : spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
4634 : {
4635 : /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
4636 : SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
4637 8 : return ctrlr->log_page_supported[log_page];
4638 : }
4639 :
4640 : bool
4641 4 : spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
4642 : {
4643 : /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
4644 : SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
4645 4 : return ctrlr->feature_supported[feature_code];
4646 : }
4647 :
4648 : int
4649 1 : spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4650 : struct spdk_nvme_ctrlr_list *payload)
4651 : {
4652 : struct nvme_completion_poll_status *status;
4653 : struct spdk_nvme_ns *ns;
4654 : int res;
4655 :
4656 1 : if (nsid == 0) {
4657 0 : return -EINVAL;
4658 : }
4659 :
4660 1 : status = calloc(1, sizeof(*status));
4661 1 : if (!status) {
4662 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4663 0 : return -ENOMEM;
4664 : }
4665 :
4666 1 : res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
4667 : nvme_completion_poll_cb, status);
4668 1 : if (res) {
4669 0 : free(status);
4670 0 : return res;
4671 : }
4672 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4673 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n");
4674 0 : if (!status->timed_out) {
4675 0 : free(status);
4676 : }
4677 0 : return -ENXIO;
4678 : }
4679 1 : free(status);
4680 :
4681 1 : res = nvme_ctrlr_identify_active_ns(ctrlr);
4682 1 : if (res) {
4683 0 : return res;
4684 : }
4685 :
4686 1 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
4687 1 : if (ns == NULL) {
4688 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n");
4689 0 : return -ENXIO;
4690 : }
4691 :
4692 1 : return nvme_ns_construct(ns, nsid, ctrlr);
4693 : }
4694 :
4695 : int
4696 1 : spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4697 : struct spdk_nvme_ctrlr_list *payload)
4698 : {
4699 : struct nvme_completion_poll_status *status;
4700 : int res;
4701 :
4702 1 : if (nsid == 0) {
4703 0 : return -EINVAL;
4704 : }
4705 :
4706 1 : status = calloc(1, sizeof(*status));
4707 1 : if (!status) {
4708 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4709 0 : return -ENOMEM;
4710 : }
4711 :
4712 1 : res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
4713 : nvme_completion_poll_cb, status);
4714 1 : if (res) {
4715 0 : free(status);
4716 0 : return res;
4717 : }
4718 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4719 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n");
4720 0 : if (!status->timed_out) {
4721 0 : free(status);
4722 : }
4723 0 : return -ENXIO;
4724 : }
4725 1 : free(status);
4726 :
4727 1 : return nvme_ctrlr_identify_active_ns(ctrlr);
4728 : }
4729 :
4730 : uint32_t
4731 1 : spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
4732 : {
4733 : struct nvme_completion_poll_status *status;
4734 : int res;
4735 : uint32_t nsid;
4736 :
4737 1 : status = calloc(1, sizeof(*status));
4738 1 : if (!status) {
4739 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4740 0 : return 0;
4741 : }
4742 :
4743 1 : res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
4744 1 : if (res) {
4745 0 : free(status);
4746 0 : return 0;
4747 : }
4748 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4749 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n");
4750 0 : if (!status->timed_out) {
4751 0 : free(status);
4752 : }
4753 0 : return 0;
4754 : }
4755 :
4756 1 : nsid = status->cpl.cdw0;
4757 1 : free(status);
4758 :
4759 1 : assert(nsid > 0);
4760 :
4761 : /* Return the namespace ID that was created */
4762 1 : return nsid;
4763 : }
4764 :
4765 : int
4766 1 : spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4767 : {
4768 : struct nvme_completion_poll_status *status;
4769 : int res;
4770 :
4771 1 : if (nsid == 0) {
4772 0 : return -EINVAL;
4773 : }
4774 :
4775 1 : status = calloc(1, sizeof(*status));
4776 1 : if (!status) {
4777 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4778 0 : return -ENOMEM;
4779 : }
4780 :
4781 1 : res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
4782 1 : if (res) {
4783 0 : free(status);
4784 0 : return res;
4785 : }
4786 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4787 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n");
4788 0 : if (!status->timed_out) {
4789 0 : free(status);
4790 : }
4791 0 : return -ENXIO;
4792 : }
4793 1 : free(status);
4794 :
4795 1 : return nvme_ctrlr_identify_active_ns(ctrlr);
4796 : }
4797 :
4798 : int
4799 0 : spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4800 : struct spdk_nvme_format *format)
4801 : {
4802 : struct nvme_completion_poll_status *status;
4803 : int res;
4804 :
4805 0 : status = calloc(1, sizeof(*status));
4806 0 : if (!status) {
4807 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4808 0 : return -ENOMEM;
4809 : }
4810 :
4811 0 : res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
4812 : status);
4813 0 : if (res) {
4814 0 : free(status);
4815 0 : return res;
4816 : }
4817 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4818 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n");
4819 0 : if (!status->timed_out) {
4820 0 : free(status);
4821 : }
4822 0 : return -ENXIO;
4823 : }
4824 0 : free(status);
4825 :
4826 0 : return spdk_nvme_ctrlr_reset(ctrlr);
4827 : }
4828 :
4829 : int
4830 8 : spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
4831 : int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
4832 : {
4833 8 : struct spdk_nvme_fw_commit fw_commit;
4834 : struct nvme_completion_poll_status *status;
4835 : int res;
4836 : unsigned int size_remaining;
4837 : unsigned int offset;
4838 : unsigned int transfer;
4839 : uint8_t *p;
4840 :
4841 8 : if (!completion_status) {
4842 0 : return -EINVAL;
4843 : }
4844 8 : memset(completion_status, 0, sizeof(struct spdk_nvme_status));
4845 8 : if (size % 4) {
4846 1 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n");
4847 1 : return -1;
4848 : }
4849 :
4850 : /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
4851 : * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
4852 : */
4853 7 : if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
4854 : (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
4855 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n");
4856 0 : return -1;
4857 : }
4858 :
4859 7 : status = calloc(1, sizeof(*status));
4860 7 : if (!status) {
4861 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4862 0 : return -ENOMEM;
4863 : }
4864 :
4865 : /* Firmware download */
4866 7 : size_remaining = size;
4867 7 : offset = 0;
4868 7 : p = payload;
4869 :
4870 10 : while (size_remaining > 0) {
4871 7 : transfer = spdk_min(size_remaining, ctrlr->min_page_size);
4872 :
4873 7 : memset(status, 0, sizeof(*status));
4874 7 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
4875 : nvme_completion_poll_cb,
4876 : status);
4877 7 : if (res) {
4878 2 : free(status);
4879 2 : return res;
4880 : }
4881 :
4882 5 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4883 2 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n");
4884 2 : if (!status->timed_out) {
4885 1 : free(status);
4886 : }
4887 2 : return -ENXIO;
4888 : }
4889 3 : p += transfer;
4890 3 : offset += transfer;
4891 3 : size_remaining -= transfer;
4892 : }
4893 :
4894 : /* Firmware commit */
4895 3 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
4896 3 : fw_commit.fs = slot;
4897 3 : fw_commit.ca = commit_action;
4898 :
4899 3 : memset(status, 0, sizeof(*status));
4900 3 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
4901 : status);
4902 3 : if (res) {
4903 1 : free(status);
4904 1 : return res;
4905 : }
4906 :
4907 2 : res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
4908 :
4909 2 : memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
4910 :
4911 2 : if (!status->timed_out) {
4912 2 : free(status);
4913 : }
4914 :
4915 2 : if (res) {
4916 1 : if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
4917 0 : completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
4918 1 : if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
4919 0 : completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
4920 0 : NVME_CTRLR_NOTICELOG(ctrlr,
4921 : "firmware activation requires conventional reset to be performed. !\n");
4922 : } else {
4923 1 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
4924 : }
4925 1 : return -ENXIO;
4926 : }
4927 : }
4928 :
4929 1 : return spdk_nvme_ctrlr_reset(ctrlr);
4930 : }
4931 :
4932 : int
4933 0 : spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
4934 : {
4935 : int rc, size;
4936 : union spdk_nvme_cmbsz_register cmbsz;
4937 :
4938 0 : cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
4939 :
4940 0 : if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
4941 0 : return -ENOTSUP;
4942 : }
4943 :
4944 0 : size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
4945 :
4946 0 : nvme_ctrlr_lock(ctrlr);
4947 0 : rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
4948 0 : nvme_ctrlr_unlock(ctrlr);
4949 :
4950 0 : if (rc < 0) {
4951 0 : return rc;
4952 : }
4953 :
4954 0 : return size;
4955 : }
4956 :
4957 : void *
4958 0 : spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
4959 : {
4960 : void *buf;
4961 :
4962 0 : nvme_ctrlr_lock(ctrlr);
4963 0 : buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
4964 0 : nvme_ctrlr_unlock(ctrlr);
4965 :
4966 0 : return buf;
4967 : }
4968 :
4969 : void
4970 0 : spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
4971 : {
4972 0 : nvme_ctrlr_lock(ctrlr);
4973 0 : nvme_transport_ctrlr_unmap_cmb(ctrlr);
4974 0 : nvme_ctrlr_unlock(ctrlr);
4975 0 : }
4976 :
4977 : int
4978 0 : spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
4979 : {
4980 : int rc;
4981 :
4982 0 : nvme_ctrlr_lock(ctrlr);
4983 0 : rc = nvme_transport_ctrlr_enable_pmr(ctrlr);
4984 0 : nvme_ctrlr_unlock(ctrlr);
4985 :
4986 0 : return rc;
4987 : }
4988 :
4989 : int
4990 0 : spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
4991 : {
4992 : int rc;
4993 :
4994 0 : nvme_ctrlr_lock(ctrlr);
4995 0 : rc = nvme_transport_ctrlr_disable_pmr(ctrlr);
4996 0 : nvme_ctrlr_unlock(ctrlr);
4997 :
4998 0 : return rc;
4999 : }
5000 :
5001 : void *
5002 0 : spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5003 : {
5004 : void *buf;
5005 :
5006 0 : nvme_ctrlr_lock(ctrlr);
5007 0 : buf = nvme_transport_ctrlr_map_pmr(ctrlr, size);
5008 0 : nvme_ctrlr_unlock(ctrlr);
5009 :
5010 0 : return buf;
5011 : }
5012 :
5013 : int
5014 0 : spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
5015 : {
5016 : int rc;
5017 :
5018 0 : nvme_ctrlr_lock(ctrlr);
5019 0 : rc = nvme_transport_ctrlr_unmap_pmr(ctrlr);
5020 0 : nvme_ctrlr_unlock(ctrlr);
5021 :
5022 0 : return rc;
5023 : }
5024 :
5025 : int
5026 0 : spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload,
5027 : uint32_t bprsz, uint32_t bprof, uint32_t bpid)
5028 : {
5029 0 : union spdk_nvme_bprsel_register bprsel;
5030 0 : union spdk_nvme_bpinfo_register bpinfo;
5031 0 : uint64_t bpmbl, bpmb_size;
5032 :
5033 0 : if (ctrlr->cap.bits.bps == 0) {
5034 0 : return -ENOTSUP;
5035 : }
5036 :
5037 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5038 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5039 0 : return -EIO;
5040 : }
5041 :
5042 0 : if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) {
5043 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n");
5044 0 : return -EALREADY;
5045 : }
5046 :
5047 0 : nvme_ctrlr_lock(ctrlr);
5048 :
5049 0 : bpmb_size = bprsz * 4096;
5050 0 : bpmbl = spdk_vtophys(payload, &bpmb_size);
5051 0 : if (bpmbl == SPDK_VTOPHYS_ERROR) {
5052 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n");
5053 0 : nvme_ctrlr_unlock(ctrlr);
5054 0 : return -EFAULT;
5055 : }
5056 :
5057 0 : if (bpmb_size != bprsz * 4096) {
5058 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n");
5059 0 : nvme_ctrlr_unlock(ctrlr);
5060 0 : return -EFAULT;
5061 : }
5062 :
5063 0 : if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) {
5064 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n");
5065 0 : nvme_ctrlr_unlock(ctrlr);
5066 0 : return -EIO;
5067 : }
5068 :
5069 0 : bprsel.bits.bpid = bpid;
5070 0 : bprsel.bits.bprof = bprof;
5071 0 : bprsel.bits.bprsz = bprsz;
5072 :
5073 0 : if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) {
5074 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n");
5075 0 : nvme_ctrlr_unlock(ctrlr);
5076 0 : return -EIO;
5077 : }
5078 :
5079 0 : nvme_ctrlr_unlock(ctrlr);
5080 0 : return 0;
5081 : }
5082 :
5083 : int
5084 0 : spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr)
5085 : {
5086 0 : int rc = 0;
5087 0 : union spdk_nvme_bpinfo_register bpinfo;
5088 :
5089 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5090 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5091 0 : return -EIO;
5092 : }
5093 :
5094 0 : switch (bpinfo.bits.brs) {
5095 0 : case SPDK_NVME_BRS_NO_READ:
5096 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n");
5097 0 : rc = -EINVAL;
5098 0 : break;
5099 0 : case SPDK_NVME_BRS_READ_IN_PROGRESS:
5100 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n");
5101 0 : rc = -EAGAIN;
5102 0 : break;
5103 0 : case SPDK_NVME_BRS_READ_ERROR:
5104 0 : NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n");
5105 0 : rc = -EIO;
5106 0 : break;
5107 0 : case SPDK_NVME_BRS_READ_SUCCESS:
5108 0 : NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n");
5109 0 : break;
5110 0 : default:
5111 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n");
5112 0 : rc = -EINVAL;
5113 : }
5114 :
5115 0 : return rc;
5116 : }
5117 :
5118 : static void
5119 0 : nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl)
5120 : {
5121 : int res;
5122 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
5123 0 : struct spdk_nvme_fw_commit fw_commit;
5124 0 : struct spdk_nvme_cpl err_cpl =
5125 : {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }};
5126 :
5127 0 : if (spdk_nvme_cpl_is_error(cpl)) {
5128 0 : NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n");
5129 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5130 0 : return;
5131 : }
5132 :
5133 0 : if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) {
5134 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset);
5135 0 : ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size;
5136 0 : ctrlr->fw_offset += ctrlr->fw_transfer_size;
5137 0 : ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size;
5138 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5139 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5140 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5141 0 : if (res) {
5142 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n");
5143 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5144 0 : return;
5145 : }
5146 :
5147 0 : if (ctrlr->fw_transfer_size < ctrlr->min_page_size) {
5148 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED;
5149 : }
5150 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) {
5151 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n");
5152 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5153 0 : fw_commit.bpid = ctrlr->bpid;
5154 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION;
5155 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5156 : nvme_write_boot_partition_cb, ctrlr);
5157 0 : if (res) {
5158 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5159 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5160 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5161 0 : return;
5162 : }
5163 :
5164 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE;
5165 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) {
5166 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n");
5167 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5168 0 : fw_commit.bpid = ctrlr->bpid;
5169 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION;
5170 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5171 : nvme_write_boot_partition_cb, ctrlr);
5172 0 : if (res) {
5173 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5174 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5175 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5176 0 : return;
5177 : }
5178 :
5179 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE;
5180 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) {
5181 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n");
5182 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5183 : } else {
5184 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n");
5185 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5186 0 : return;
5187 : }
5188 : }
5189 :
5190 : int
5191 0 : spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr,
5192 : void *payload, uint32_t size, uint32_t bpid,
5193 : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
5194 : {
5195 : int res;
5196 :
5197 0 : if (ctrlr->cap.bits.bps == 0) {
5198 0 : return -ENOTSUP;
5199 : }
5200 :
5201 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING;
5202 0 : ctrlr->bpid = bpid;
5203 0 : ctrlr->bp_write_cb_fn = cb_fn;
5204 0 : ctrlr->bp_write_cb_arg = cb_arg;
5205 0 : ctrlr->fw_offset = 0;
5206 0 : ctrlr->fw_size_remaining = size;
5207 0 : ctrlr->fw_payload = payload;
5208 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5209 :
5210 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5211 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5212 :
5213 0 : return res;
5214 : }
5215 :
5216 : bool
5217 43 : spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
5218 : {
5219 43 : assert(ctrlr);
5220 :
5221 43 : return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
5222 : strlen(SPDK_NVMF_DISCOVERY_NQN));
5223 : }
5224 :
5225 : bool
5226 20 : spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr)
5227 : {
5228 20 : assert(ctrlr);
5229 :
5230 20 : return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype);
5231 : }
5232 :
5233 : int
5234 0 : spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5235 : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5236 : {
5237 : struct nvme_completion_poll_status *status;
5238 : int res;
5239 :
5240 0 : status = calloc(1, sizeof(*status));
5241 0 : if (!status) {
5242 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5243 0 : return -ENOMEM;
5244 : }
5245 :
5246 0 : res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
5247 : nvme_completion_poll_cb, status);
5248 0 : if (res) {
5249 0 : free(status);
5250 0 : return res;
5251 : }
5252 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5253 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n");
5254 0 : if (!status->timed_out) {
5255 0 : free(status);
5256 : }
5257 0 : return -ENXIO;
5258 : }
5259 0 : free(status);
5260 :
5261 0 : return 0;
5262 : }
5263 :
5264 : int
5265 0 : spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5266 : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5267 : {
5268 : struct nvme_completion_poll_status *status;
5269 : int res;
5270 :
5271 0 : status = calloc(1, sizeof(*status));
5272 0 : if (!status) {
5273 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5274 0 : return -ENOMEM;
5275 : }
5276 :
5277 0 : res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
5278 : nvme_completion_poll_cb,
5279 : status);
5280 0 : if (res) {
5281 0 : free(status);
5282 0 : return res;
5283 : }
5284 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5285 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n");
5286 0 : if (!status->timed_out) {
5287 0 : free(status);
5288 : }
5289 0 : return -ENXIO;
5290 : }
5291 :
5292 0 : free(status);
5293 :
5294 0 : return 0;
5295 : }
5296 :
5297 : uint64_t
5298 1 : spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
5299 : {
5300 1 : return ctrlr->flags;
5301 : }
5302 :
5303 : const struct spdk_nvme_transport_id *
5304 0 : spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
5305 : {
5306 0 : return &ctrlr->trid;
5307 : }
5308 :
5309 : int32_t
5310 17 : spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
5311 : {
5312 : uint32_t qid;
5313 :
5314 17 : assert(ctrlr->free_io_qids);
5315 17 : nvme_ctrlr_lock(ctrlr);
5316 17 : qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
5317 17 : if (qid > ctrlr->opts.num_io_queues) {
5318 2 : NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n");
5319 2 : nvme_ctrlr_unlock(ctrlr);
5320 2 : return -1;
5321 : }
5322 :
5323 15 : spdk_bit_array_clear(ctrlr->free_io_qids, qid);
5324 15 : nvme_ctrlr_unlock(ctrlr);
5325 15 : return qid;
5326 : }
5327 :
5328 : void
5329 64 : spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
5330 : {
5331 64 : assert(qid <= ctrlr->opts.num_io_queues);
5332 :
5333 64 : nvme_ctrlr_lock(ctrlr);
5334 :
5335 64 : if (spdk_likely(ctrlr->free_io_qids)) {
5336 64 : spdk_bit_array_set(ctrlr->free_io_qids, qid);
5337 : }
5338 :
5339 64 : nvme_ctrlr_unlock(ctrlr);
5340 64 : }
5341 :
5342 : int
5343 2 : spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
5344 : struct spdk_memory_domain **domains, int array_size)
5345 : {
5346 2 : return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size);
5347 : }
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