Branch data Line data Source code
1 : : /* SPDX-License-Identifier: BSD-3-Clause
2 : : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : : * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.
4 : : * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : : */
6 : :
7 : : #include "spdk/stdinc.h"
8 : :
9 : : #include "nvme_internal.h"
10 : : #include "nvme_io_msg.h"
11 : :
12 : : #include "spdk/env.h"
13 : : #include "spdk/string.h"
14 : : #include "spdk/endian.h"
15 : :
16 : : struct nvme_active_ns_ctx;
17 : :
18 : : static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
19 : : struct nvme_async_event_request *aer);
20 : : static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
21 : : static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
22 : : static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
23 : : static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
24 : : static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr);
25 : : static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
26 : : uint64_t timeout_in_ms);
27 : :
28 : : static int
29 : 1460454 : nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2)
30 : : {
31 [ + + + - : 1460454 : if (ns1->id < ns2->id) {
+ - + - -
+ ]
32 : 495242 : return -1;
33 [ + + + - : 965212 : } else if (ns1->id > ns2->id) {
+ - + - -
+ ]
34 : 829905 : return 1;
35 : : } else {
36 : 135307 : return 0;
37 : : }
38 : 4091 : }
39 : :
40 [ + + + + : 1901017 : RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp);
+ + + + +
+ + + + +
+ + + + -
- + - + -
+ + + + +
+ + + + +
+ + - + -
+ + + + +
- + + + +
- + - + -
- + - - -
- + + # #
# # # # #
# # # # #
# # + - +
- + - + -
# # # # #
# # # # #
# # - + #
# # # # #
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - -
+ # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # + - +
- + - - +
+ - + - #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # - + #
# # # # #
# # # # #
# - + - +
+ - + - +
+ + - # #
# # # # -
+ # # # #
# # + - +
- - + # #
# # # # #
# # # # #
# # # # +
- + - + -
+ - + - +
- + - + -
+ - - + +
- + - # #
# # # # #
# # # # #
# # - + #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # + - +
- + - + -
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
41 : :
42 : : #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \
43 : : nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
44 : : offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
45 : :
46 : : #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \
47 : : nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \
48 : : offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg)
49 : :
50 : : #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \
51 : : nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg)
52 : :
53 : : #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \
54 : : nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg)
55 : :
56 : : #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
57 : : nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
58 : :
59 : : #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
60 : : nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
61 : :
62 : : #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \
63 : : nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg)
64 : :
65 : : static int
66 : 0 : nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
67 : : {
68 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
69 [ # # ]: 0 : &cc->raw);
70 : : }
71 : :
72 : : static int
73 : 32517 : nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
74 : : {
75 : 32517 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
76 [ + - ]: 33 : &csts->raw);
77 : : }
78 : :
79 : : int
80 : 794 : nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
81 : : {
82 : 794 : return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
83 [ + - ]: 9 : &cap->raw);
84 : : }
85 : :
86 : : int
87 : 3 : nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
88 : : {
89 : 3 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
90 [ # # ]: 0 : &vs->raw);
91 : : }
92 : :
93 : : int
94 : 8 : nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
95 : : {
96 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
97 [ # # ]: 0 : &cmbsz->raw);
98 : : }
99 : :
100 : : int
101 : 8 : nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
102 : : {
103 : 8 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
104 [ # # ]: 0 : &pmrcap->raw);
105 : : }
106 : :
107 : : int
108 : 0 : nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo)
109 : : {
110 : 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw),
111 [ # # ]: 0 : &bpinfo->raw);
112 : : }
113 : :
114 : : int
115 : 0 : nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel)
116 : : {
117 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw),
118 [ # # # # ]: 0 : bprsel->raw);
119 : : }
120 : :
121 : : int
122 : 0 : nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value)
123 : : {
124 : 0 : return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl),
125 : 0 : bpmbl_value);
126 : : }
127 : :
128 : : static int
129 : 0 : nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
130 : : {
131 : 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
132 : 0 : nssr_value);
133 : : }
134 : :
135 : : bool
136 : 6826 : nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
137 : : {
138 [ + + + - : 8806 : return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
+ - + - +
- ]
139 [ + + # # : 1980 : ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
# # ]
140 : : }
141 : :
142 : : /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
143 : : * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
144 : : */
145 : : void
146 : 5205 : spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
147 : : {
148 [ + + # # ]: 5205 : assert(opts);
149 : :
150 [ + - + - ]: 5205 : opts->opts_size = opts_size;
151 : :
152 : : #define FIELD_OK(field) \
153 : : offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
154 : :
155 : : #define SET_FIELD(field, value) \
156 : : if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
157 : : opts->field = value; \
158 : : } \
159 : :
160 [ + + + - : 5205 : SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
+ - ]
161 [ + + + - : 5205 : SET_FIELD(use_cmb_sqs, false);
+ - ]
162 [ + + + - : 5205 : SET_FIELD(no_shn_notification, false);
+ - ]
163 [ + + + - : 5205 : SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
+ - ]
164 [ + + + - : 5205 : SET_FIELD(arbitration_burst, 0);
+ - ]
165 [ + + + - : 5205 : SET_FIELD(low_priority_weight, 0);
+ - ]
166 [ + + + - : 5205 : SET_FIELD(medium_priority_weight, 0);
+ - ]
167 [ + + + - : 5205 : SET_FIELD(high_priority_weight, 0);
+ - ]
168 [ + + + - : 5205 : SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
+ - ]
169 [ + + + - : 5205 : SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
+ - ]
170 [ + + + - : 5205 : SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
+ - ]
171 : :
172 [ + + ]: 5205 : if (nvme_driver_init() == 0) {
173 [ + + ]: 5205 : if (FIELD_OK(hostnqn)) {
174 [ + - ]: 5202 : nvme_get_default_hostnqn(opts->hostnqn, sizeof(opts->hostnqn));
175 : 818 : }
176 : :
177 [ + + ]: 5205 : if (FIELD_OK(extended_host_id)) {
178 [ + - + - : 5202 : memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
+ - + - ]
179 : : sizeof(opts->extended_host_id));
180 : 818 : }
181 : :
182 : 818 : }
183 : :
184 [ + + + - : 5205 : SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
+ - ]
185 : :
186 [ + + ]: 5205 : if (FIELD_OK(src_addr)) {
187 [ + + + - ]: 5202 : memset(opts->src_addr, 0, sizeof(opts->src_addr));
188 : 818 : }
189 : :
190 [ + + ]: 5205 : if (FIELD_OK(src_svcid)) {
191 [ + + + - ]: 5202 : memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
192 : 818 : }
193 : :
194 [ + + ]: 5205 : if (FIELD_OK(host_id)) {
195 [ + + + - ]: 5202 : memset(opts->host_id, 0, sizeof(opts->host_id));
196 : 818 : }
197 : :
198 [ + + + - : 5205 : SET_FIELD(command_set, CHAR_BIT);
+ - ]
199 [ + + + - : 5205 : SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
+ - ]
200 [ + + + - : 5205 : SET_FIELD(header_digest, false);
+ - ]
201 [ + + + - : 5205 : SET_FIELD(data_digest, false);
+ - ]
202 [ + + + - : 5205 : SET_FIELD(disable_error_logging, false);
+ - ]
203 [ + + + - : 5205 : SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
+ - ]
204 [ + + + - : 5205 : SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
+ - ]
205 [ + + + - : 5205 : SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
+ - ]
206 [ + + + - : 5205 : SET_FIELD(disable_read_ana_log_page, false);
+ - ]
207 [ + + + - : 5205 : SET_FIELD(disable_read_changed_ns_list_log_page, false);
+ - ]
208 [ + + + - : 5205 : SET_FIELD(tls_psk, NULL);
+ - ]
209 [ + + + - : 5205 : SET_FIELD(dhchap_key, NULL);
+ - ]
210 [ + + + - : 5205 : SET_FIELD(dhchap_ctrlr_key, NULL);
+ - ]
211 [ + + + - : 5205 : SET_FIELD(dhchap_digests,
+ - + - +
- + - ]
212 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA256) |
213 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA384) |
214 : : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA512));
215 [ + + + - : 5205 : SET_FIELD(dhchap_dhgroups,
+ - + - +
- + - + -
+ - + - ]
216 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_NULL) |
217 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_2048) |
218 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_3072) |
219 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_4096) |
220 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_6144) |
221 : : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_8192));
222 : : #undef FIELD_OK
223 : : #undef SET_FIELD
224 : 5205 : }
225 : :
226 : : const struct spdk_nvme_ctrlr_opts *
227 : 3052 : spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr)
228 : : {
229 [ + - ]: 3052 : return &ctrlr->opts;
230 : : }
231 : :
232 : : /**
233 : : * This function will be called when the process allocates the IO qpair.
234 : : * Note: the ctrlr_lock must be held when calling this function.
235 : : */
236 : : static void
237 : 5987 : nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
238 : : {
239 : : struct spdk_nvme_ctrlr_process *active_proc;
240 [ + - + - ]: 5987 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
241 : :
242 : 5987 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
243 [ + + ]: 5987 : if (active_proc) {
244 [ + - + - : 5942 : TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - ]
245 [ + - + - ]: 5942 : qpair->active_proc = active_proc;
246 : 817 : }
247 : 5987 : }
248 : :
249 : : /**
250 : : * This function will be called when the process frees the IO qpair.
251 : : * Note: the ctrlr_lock must be held when calling this function.
252 : : */
253 : : static void
254 : 5987 : nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
255 : : {
256 : : struct spdk_nvme_ctrlr_process *active_proc;
257 [ + - + - ]: 5987 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
258 : : struct spdk_nvme_qpair *active_qpair, *tmp_qpair;
259 : :
260 : 5987 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
261 [ + + ]: 5987 : if (!active_proc) {
262 : 45 : return;
263 : : }
264 : :
265 [ + - + - : 6333 : TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
+ - - + +
- + - + -
- + ]
266 : : per_process_tailq, tmp_qpair) {
267 [ + + ]: 6333 : if (active_qpair == qpair) {
268 [ + + + - : 5942 : TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
+ - - + #
# # # # #
# # # # #
# # # # #
# # - + -
+ - + - +
- + - + +
- + - + -
+ - + - +
- + - ]
269 : : active_qpair, per_process_tailq);
270 : :
271 : 5942 : break;
272 : : }
273 : 0 : }
274 : 817 : }
275 : :
276 : : void
277 : 9051 : spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
278 : : struct spdk_nvme_io_qpair_opts *opts,
279 : : size_t opts_size)
280 : : {
281 [ + + # # ]: 9051 : assert(ctrlr);
282 : :
283 [ + + # # ]: 9051 : assert(opts);
284 : :
285 [ + + ]: 9051 : memset(opts, 0, opts_size);
286 : :
287 : : #define FIELD_OK(field) \
288 : : offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
289 : :
290 [ + + ]: 9051 : if (FIELD_OK(qprio)) {
291 [ + - + - ]: 9051 : opts->qprio = SPDK_NVME_QPRIO_URGENT;
292 : 818 : }
293 : :
294 [ + + ]: 9051 : if (FIELD_OK(io_queue_size)) {
295 [ + - + - : 9051 : opts->io_queue_size = ctrlr->opts.io_queue_size;
+ - + - +
- ]
296 : 818 : }
297 : :
298 [ + + ]: 9051 : if (FIELD_OK(io_queue_requests)) {
299 [ + - + - : 9048 : opts->io_queue_requests = ctrlr->opts.io_queue_requests;
+ - + - +
- ]
300 : 818 : }
301 : :
302 [ + + ]: 9051 : if (FIELD_OK(delay_cmd_submit)) {
303 [ + - + - : 9048 : opts->delay_cmd_submit = false;
+ - ]
304 : 818 : }
305 : :
306 [ + + ]: 9051 : if (FIELD_OK(sq.vaddr)) {
307 [ + - + - : 9048 : opts->sq.vaddr = NULL;
+ - ]
308 : 818 : }
309 : :
310 [ + + ]: 9051 : if (FIELD_OK(sq.paddr)) {
311 [ + - + - : 9048 : opts->sq.paddr = 0;
+ - ]
312 : 818 : }
313 : :
314 [ + + ]: 9051 : if (FIELD_OK(sq.buffer_size)) {
315 [ + - + - : 9048 : opts->sq.buffer_size = 0;
+ - ]
316 : 818 : }
317 : :
318 [ + + ]: 9051 : if (FIELD_OK(cq.vaddr)) {
319 [ + - + - : 9048 : opts->cq.vaddr = NULL;
+ - ]
320 : 818 : }
321 : :
322 [ + + ]: 9051 : if (FIELD_OK(cq.paddr)) {
323 [ + - + - : 9048 : opts->cq.paddr = 0;
+ - ]
324 : 818 : }
325 : :
326 [ + + ]: 9051 : if (FIELD_OK(cq.buffer_size)) {
327 [ + - + - : 9048 : opts->cq.buffer_size = 0;
+ - ]
328 : 818 : }
329 : :
330 [ + + ]: 9051 : if (FIELD_OK(create_only)) {
331 [ + - + - ]: 9048 : opts->create_only = false;
332 : 818 : }
333 : :
334 [ + + ]: 9051 : if (FIELD_OK(async_mode)) {
335 [ + - + - ]: 9048 : opts->async_mode = false;
336 : 818 : }
337 : :
338 : : #undef FIELD_OK
339 : 9051 : }
340 : :
341 : : static struct spdk_nvme_qpair *
342 : 6010 : nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
343 : : const struct spdk_nvme_io_qpair_opts *opts)
344 : : {
345 : : int32_t qid;
346 : : struct spdk_nvme_qpair *qpair;
347 : : union spdk_nvme_cc_register cc;
348 : :
349 [ + + ]: 6010 : if (!ctrlr) {
350 : 0 : return NULL;
351 : : }
352 : :
353 : 6010 : nvme_ctrlr_lock(ctrlr);
354 [ + - + - : 6010 : cc.raw = ctrlr->process_init_cc.raw;
+ - ]
355 : :
356 [ + + + - : 6010 : if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
- + ]
357 : 6 : nvme_ctrlr_unlock(ctrlr);
358 : 6 : return NULL;
359 : : }
360 : :
361 : : /*
362 : : * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
363 : : * default round robin arbitration method.
364 : : */
365 [ + + + + : 6004 : if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
+ - + - ]
366 [ + - # # : 9 : NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n");
# # # # #
# # # # #
# # # # #
# ]
367 : 9 : nvme_ctrlr_unlock(ctrlr);
368 : 9 : return NULL;
369 : : }
370 : :
371 : 5995 : qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
372 [ + + ]: 5995 : if (qid < 0) {
373 : 8 : nvme_ctrlr_unlock(ctrlr);
374 : 8 : return NULL;
375 : : }
376 : :
377 : 5987 : qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
378 [ + + ]: 5987 : if (qpair == NULL) {
379 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n");
# # # # #
# # # # #
# # # # #
# ]
380 : 0 : spdk_nvme_ctrlr_free_qid(ctrlr, qid);
381 : 0 : nvme_ctrlr_unlock(ctrlr);
382 : 0 : return NULL;
383 : : }
384 : :
385 [ + - + - : 5987 : TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - ]
386 : :
387 : 5987 : nvme_ctrlr_proc_add_io_qpair(qpair);
388 : :
389 : 5987 : nvme_ctrlr_unlock(ctrlr);
390 : :
391 : 5987 : return qpair;
392 : 817 : }
393 : :
394 : : int
395 : 5987 : spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
396 : : {
397 : : int rc;
398 : :
399 [ - + ]: 5987 : if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
400 : 0 : return -EISCONN;
401 : : }
402 : :
403 : 5987 : nvme_ctrlr_lock(ctrlr);
404 : 5987 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
405 : 5987 : nvme_ctrlr_unlock(ctrlr);
406 : :
407 [ + + + - : 5987 : if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
+ - ]
408 : 0 : spdk_delay_us(100);
409 : 0 : }
410 : :
411 : 5987 : return rc;
412 : 817 : }
413 : :
414 : : void
415 : 2285 : spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
416 : : {
417 [ + - + - ]: 2285 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
418 : :
419 : 2285 : nvme_ctrlr_lock(ctrlr);
420 : 2285 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
421 : 2285 : nvme_ctrlr_unlock(ctrlr);
422 : 2285 : }
423 : :
424 : : struct spdk_nvme_qpair *
425 : 6013 : spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
426 : : const struct spdk_nvme_io_qpair_opts *user_opts,
427 : : size_t opts_size)
428 : : {
429 : :
430 : 6013 : struct spdk_nvme_qpair *qpair = NULL;
431 : 974 : struct spdk_nvme_io_qpair_opts opts;
432 : : int rc;
433 : :
434 : 6013 : nvme_ctrlr_lock(ctrlr);
435 : :
436 [ + + + - : 6013 : if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) {
- + ]
437 : : /* When controller is resetting or initializing, free_io_qids is deleted or not created yet.
438 : : * We can't create IO qpair in that case */
439 : 3 : goto unlock;
440 : : }
441 : :
442 : : /*
443 : : * Get the default options, then overwrite them with the user-provided options
444 : : * up to opts_size.
445 : : *
446 : : * This allows for extensions of the opts structure without breaking
447 : : * ABI compatibility.
448 : : */
449 : 6010 : spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
450 [ + + ]: 6010 : if (user_opts) {
451 [ - + + - : 3181 : memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
+ - ]
452 : :
453 : : /* If user passes buffers, make sure they're big enough for the requested queue size */
454 [ + + + - : 3181 : if (opts.sq.vaddr) {
+ - ]
455 [ # # # # : 0 : if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
# # # # ]
456 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
457 : : opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
458 : 0 : goto unlock;
459 : : }
460 : 0 : }
461 [ + + + - : 3181 : if (opts.cq.vaddr) {
+ - ]
462 [ # # # # : 0 : if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
# # # # ]
463 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
464 : : opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
465 : 0 : goto unlock;
466 : : }
467 : 0 : }
468 : 1 : }
469 : :
470 : 6010 : qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
471 : :
472 [ + + + + : 6010 : if (qpair == NULL || opts.create_only == true) {
+ + + + ]
473 : 2726 : goto unlock;
474 : : }
475 : :
476 : 3284 : rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
477 [ + + ]: 3284 : if (rc != 0) {
478 [ + - # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n");
# # # # #
# # # # #
# # # # #
# ]
479 : 3 : nvme_ctrlr_proc_remove_io_qpair(qpair);
480 [ - + # # : 3 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
481 [ # # # # : 3 : spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
# # # # ]
482 : 3 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
483 : 3 : qpair = NULL;
484 : 3 : goto unlock;
485 : : }
486 : :
487 : 3287 : unlock:
488 : 6013 : nvme_ctrlr_unlock(ctrlr);
489 : :
490 : 6013 : return qpair;
491 : : }
492 : :
493 : : int
494 : 1050937 : spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
495 : : {
496 : : struct spdk_nvme_ctrlr *ctrlr;
497 : : enum nvme_qpair_state qpair_state;
498 : : int rc;
499 : :
500 [ - + # # ]: 1050937 : assert(qpair != NULL);
501 [ - + # # ]: 1050937 : assert(nvme_qpair_is_admin_queue(qpair) == false);
502 [ - + # # : 1050937 : assert(qpair->ctrlr != NULL);
# # # # ]
503 : :
504 [ # # # # ]: 1050937 : ctrlr = qpair->ctrlr;
505 : 1050937 : nvme_ctrlr_lock(ctrlr);
506 : 1050937 : qpair_state = nvme_qpair_get_state(qpair);
507 : :
508 [ + + + + : 1050937 : if (ctrlr->is_removed) {
# # # # ]
509 : 6 : rc = -ENODEV;
510 : 6 : goto out;
511 : : }
512 : :
513 [ + + + + : 1050931 : if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
- + # # #
# ]
514 : 6 : rc = -EAGAIN;
515 : 6 : goto out;
516 : : }
517 : :
518 [ + + + + : 1050925 : if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
- + # # #
# ]
519 : 1035549 : rc = -ENXIO;
520 : 1035549 : goto out;
521 : : }
522 : :
523 [ + + ]: 15376 : if (qpair_state != NVME_QPAIR_DISCONNECTED) {
524 : 3 : rc = 0;
525 : 3 : goto out;
526 : : }
527 : :
528 : 15373 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
529 [ + + ]: 15373 : if (rc) {
530 : 15363 : rc = -EAGAIN;
531 : 15363 : goto out;
532 : : }
533 : :
534 : 10 : out:
535 : 1050937 : nvme_ctrlr_unlock(ctrlr);
536 : 1050937 : return rc;
537 : : }
538 : :
539 : : spdk_nvme_qp_failure_reason
540 : 1261034 : spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
541 : : {
542 [ + - + - : 1261034 : return ctrlr->adminq->transport_failure_reason;
+ - ]
543 : : }
544 : :
545 : : /*
546 : : * This internal function will attempt to take the controller
547 : : * lock before calling disconnect on a controller qpair.
548 : : * Functions already holding the controller lock should
549 : : * call nvme_transport_ctrlr_disconnect_qpair directly.
550 : : */
551 : : void
552 : 30988 : nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
553 : : {
554 [ # # # # ]: 30988 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
555 : :
556 [ - + # # ]: 30988 : assert(ctrlr != NULL);
557 : 30988 : nvme_ctrlr_lock(ctrlr);
558 : 30988 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
559 : 30988 : nvme_ctrlr_unlock(ctrlr);
560 : 30988 : }
561 : :
562 : : int
563 : 5984 : spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
564 : : {
565 : : struct spdk_nvme_ctrlr *ctrlr;
566 : :
567 [ + + ]: 5984 : if (qpair == NULL) {
568 : 0 : return 0;
569 : : }
570 : :
571 [ + - + - ]: 5984 : ctrlr = qpair->ctrlr;
572 : :
573 [ + + - + ]: 5984 : if (qpair->in_completion_context) {
574 : : /*
575 : : * There are many cases where it is convenient to delete an io qpair in the context
576 : : * of that qpair's completion routine. To handle this properly, set a flag here
577 : : * so that the completion routine will perform an actual delete after the context
578 : : * unwinds.
579 : : */
580 [ # # ]: 0 : qpair->delete_after_completion_context = 1;
581 : 0 : return 0;
582 : : }
583 : :
584 [ + + + - : 5984 : if (qpair->auth.cb_fn != NULL) {
+ - + - ]
585 [ # # # # : 0 : qpair->auth.cb_fn(qpair->auth.cb_ctx, -ECANCELED);
# # # # #
# # # # #
# # ]
586 [ # # # # : 0 : qpair->auth.cb_fn = NULL;
# # ]
587 : 0 : }
588 : :
589 [ + - ]: 5984 : qpair->destroy_in_progress = 1;
590 : :
591 : 5984 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
592 : :
593 [ + + + - : 5984 : if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) {
+ + + - +
- + - ]
594 [ + - + - : 2703 : spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
+ - + - ]
595 : 1 : }
596 : :
597 : : /* Do not retry. */
598 : 5984 : nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
599 : :
600 : : /* In the multi-process case, a process may call this function on a foreign
601 : : * I/O qpair (i.e. one that this process did not create) when that qpairs process
602 : : * exits unexpectedly. In that case, we must not try to abort any reqs associated
603 : : * with that qpair, since the callbacks will also be foreign to this process.
604 : : */
605 [ + - + - : 5984 : if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
- + ]
606 : 5984 : nvme_qpair_abort_all_queued_reqs(qpair);
607 : 817 : }
608 : :
609 : 5984 : nvme_ctrlr_lock(ctrlr);
610 : :
611 : 5984 : nvme_ctrlr_proc_remove_io_qpair(qpair);
612 : :
613 [ + + + - : 5984 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
+ - - + #
# # # # #
# # # # #
# # # # #
# # + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - ]
614 [ + - + - ]: 5984 : spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
615 : :
616 : 5984 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
617 : 5984 : nvme_ctrlr_unlock(ctrlr);
618 : 5984 : return 0;
619 : 817 : }
620 : :
621 : : static void
622 : 129 : nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
623 : : struct spdk_nvme_intel_log_page_directory *log_page_directory)
624 : : {
625 [ + + ]: 129 : if (log_page_directory == NULL) {
626 : 0 : return;
627 : : }
628 : :
629 [ + + + - : 129 : assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL);
+ - + - #
# ]
630 : :
631 [ + - + - : 129 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
+ - + - ]
632 : :
633 [ + + + - : 129 : if (log_page_directory->read_latency_log_len ||
- + # # ]
634 [ + + # # ]: 11 : (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
635 [ + - + - : 121 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
+ - + - ]
636 : 2 : }
637 [ + + + - : 129 : if (log_page_directory->write_latency_log_len ||
- + # # ]
638 [ + + # # ]: 11 : (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
639 [ + - + - : 121 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
+ - + - ]
640 : 2 : }
641 [ + + + - : 129 : if (log_page_directory->temperature_statistics_log_len) {
- + ]
642 [ + - + - : 126 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
+ - + - ]
643 : 2 : }
644 [ + + + - : 129 : if (log_page_directory->smart_log_len) {
- + ]
645 [ + - + - : 123 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
+ - + - ]
646 : 2 : }
647 [ + + + - : 129 : if (log_page_directory->marketing_description_log_len) {
- + ]
648 [ + - + - : 123 : ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
+ - + - ]
649 : 2 : }
650 : 2 : }
651 : :
652 : : struct intel_log_pages_ctx {
653 : : struct spdk_nvme_intel_log_page_directory log_page_directory;
654 : : struct spdk_nvme_ctrlr *ctrlr;
655 : : };
656 : :
657 : : static void
658 : 123 : nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl)
659 : : {
660 : 123 : struct intel_log_pages_ctx *ctx = arg;
661 [ + - + - ]: 123 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
662 : :
663 [ + - + - : 123 : if (!spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ - ]
664 [ + - ]: 123 : nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory);
665 : 2 : }
666 : :
667 : 125 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
668 [ + - + - : 123 : ctrlr->opts.admin_timeout_ms);
+ - ]
669 : 123 : free(ctx);
670 : 123 : }
671 : :
672 : : static int
673 : 123 : nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
674 : : {
675 : 123 : int rc = 0;
676 : : struct intel_log_pages_ctx *ctx;
677 : :
678 : 123 : ctx = calloc(1, sizeof(*ctx));
679 [ + + ]: 123 : if (!ctx) {
680 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
681 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
682 : 0 : return 0;
683 : : }
684 : :
685 [ + - + - ]: 123 : ctx->ctrlr = ctrlr;
686 : :
687 : 123 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
688 [ + - ]: 123 : SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory,
689 : : sizeof(struct spdk_nvme_intel_log_page_directory),
690 : 2 : 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx);
691 [ - + ]: 123 : if (rc != 0) {
692 : 0 : free(ctx);
693 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
694 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
695 : 0 : return 0;
696 : : }
697 : :
698 : 125 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES,
699 [ - + - + : 123 : ctrlr->opts.admin_timeout_ms);
- + ]
700 : :
701 : 123 : return 0;
702 : 2 : }
703 : :
704 : : static int
705 : 25 : nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
706 : : {
707 : : uint32_t ana_log_page_size;
708 : :
709 [ # # # # : 25 : ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
# # ]
710 [ # # # # ]: 25 : sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count *
711 : : sizeof(uint32_t);
712 : :
713 : : /* Number of active namespaces may have changed.
714 : : * Check if ANA log page fits into existing buffer.
715 : : */
716 [ + - # # : 25 : if (ana_log_page_size > ctrlr->ana_log_page_size) {
# # ]
717 : : void *new_buffer;
718 : :
719 [ + + # # : 25 : if (ctrlr->ana_log_page) {
# # ]
720 [ # # # # ]: 3 : new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size);
721 : 0 : } else {
722 : 22 : new_buffer = calloc(1, ana_log_page_size);
723 : : }
724 : :
725 [ - + ]: 25 : if (!new_buffer) {
726 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n",
# # # # #
# # # # #
# # # # #
# ]
727 : : ana_log_page_size);
728 : 0 : return -ENXIO;
729 : : }
730 : :
731 [ # # # # ]: 25 : ctrlr->ana_log_page = new_buffer;
732 [ + + # # : 25 : if (ctrlr->copied_ana_desc) {
# # ]
733 [ # # # # ]: 3 : new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size);
734 : 0 : } else {
735 : 22 : new_buffer = calloc(1, ana_log_page_size);
736 : : }
737 : :
738 [ - + ]: 25 : if (!new_buffer) {
739 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n",
# # # # #
# # # # #
# # # # #
# ]
740 : : ana_log_page_size);
741 : 0 : return -ENOMEM;
742 : : }
743 : :
744 [ # # # # ]: 25 : ctrlr->copied_ana_desc = new_buffer;
745 [ # # # # ]: 25 : ctrlr->ana_log_page_size = ana_log_page_size;
746 : 0 : }
747 : :
748 : 25 : return 0;
749 : 0 : }
750 : :
751 : : static int
752 : 25 : nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
753 : : {
754 : : struct nvme_completion_poll_status *status;
755 : : int rc;
756 : :
757 : 25 : rc = nvme_ctrlr_alloc_ana_log_page(ctrlr);
758 [ - + ]: 25 : if (rc != 0) {
759 : 0 : return rc;
760 : : }
761 : :
762 : 25 : status = calloc(1, sizeof(*status));
763 [ - + ]: 25 : if (status == NULL) {
764 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
765 : 0 : return -ENOMEM;
766 : : }
767 : :
768 : 25 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
769 [ # # # # ]: 25 : SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
770 [ # # # # ]: 0 : ctrlr->ana_log_page_size, 0,
771 : 0 : nvme_completion_poll_cb, status);
772 [ - + ]: 25 : if (rc != 0) {
773 : 0 : free(status);
774 : 0 : return rc;
775 : : }
776 : :
777 [ - + # # : 25 : if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
# # # # ]
778 [ # # # # : 25 : ctrlr->opts.admin_timeout_ms * 1000)) {
# # ]
779 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
780 : 0 : free(status);
781 : 0 : }
782 : 0 : return -EIO;
783 : : }
784 : :
785 : 25 : free(status);
786 : 25 : return 0;
787 : 0 : }
788 : :
789 : : static int
790 : 28 : nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
791 : : void *cb_arg)
792 : : {
793 : 28 : struct spdk_nvme_ctrlr *ctrlr = cb_arg;
794 : : struct spdk_nvme_ns *ns;
795 : : uint32_t i, nsid;
796 : :
797 [ + + # # : 68 : for (i = 0; i < desc->num_of_nsid; i++) {
# # ]
798 [ # # # # : 40 : nsid = desc->nsid[i];
# # ]
799 [ + - - + : 40 : if (nsid == 0 || nsid > ctrlr->cdata.nn) {
# # # # #
# ]
800 : 0 : continue;
801 : : }
802 : :
803 : 40 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
804 [ - + # # ]: 40 : assert(ns != NULL);
805 : :
806 [ # # # # : 40 : ns->ana_group_id = desc->ana_group_id;
# # # # ]
807 [ # # # # : 40 : ns->ana_state = desc->ana_state;
# # ]
808 : 0 : }
809 : :
810 : 28 : return 0;
811 : : }
812 : :
813 : : int
814 : 25 : nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
815 : : spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
816 : : {
817 : : struct spdk_nvme_ana_group_descriptor *copied_desc;
818 : : uint8_t *orig_desc;
819 : : uint32_t i, desc_size, copy_len;
820 : 25 : int rc = 0;
821 : :
822 [ - + # # : 25 : if (ctrlr->ana_log_page == NULL) {
# # ]
823 : 0 : return -EINVAL;
824 : : }
825 : :
826 [ # # # # ]: 25 : copied_desc = ctrlr->copied_ana_desc;
827 : :
828 [ # # # # : 25 : orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page);
# # ]
829 [ # # # # ]: 25 : copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page);
830 : :
831 [ + + # # : 53 : for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
# # # # #
# ]
832 [ - + - + ]: 28 : memcpy(copied_desc, orig_desc, copy_len);
833 : :
834 [ # # # # ]: 28 : rc = cb_fn(copied_desc, cb_arg);
835 [ - + ]: 28 : if (rc != 0) {
836 : 0 : break;
837 : : }
838 : :
839 : 28 : desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) +
840 [ # # # # ]: 28 : copied_desc->num_of_nsid * sizeof(uint32_t);
841 [ # # ]: 28 : orig_desc += desc_size;
842 : 28 : copy_len -= desc_size;
843 : 0 : }
844 : :
845 : 25 : return rc;
846 : 0 : }
847 : :
848 : : static int
849 : 3293 : nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
850 : : {
851 : 3293 : int rc = 0;
852 : :
853 [ + + + - ]: 3293 : memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
854 : : /* Mandatory pages */
855 [ + - + - : 3293 : ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
+ - + - ]
856 [ + - + - : 3293 : ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
+ - + - ]
857 [ + - + - : 3293 : ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
+ - + - ]
858 [ + + + - : 3293 : if (ctrlr->cdata.lpa.celp) {
+ - - + ]
859 [ + - + - : 3248 : ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
+ - + - ]
860 : 817 : }
861 : :
862 [ + + + - : 3293 : if (ctrlr->cdata.cmic.ana_reporting) {
+ - + - ]
863 [ # # # # : 345 : ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
# # # # ]
864 [ + + + + : 345 : if (!ctrlr->opts.disable_read_ana_log_page) {
# # # # #
# ]
865 : 19 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
866 [ + - ]: 19 : if (rc == 0) {
867 : 19 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
868 : 0 : ctrlr);
869 : 0 : }
870 : 0 : }
871 : 0 : }
872 : :
873 [ + + + - : 3293 : if (ctrlr->cdata.ctratt.bits.fdps) {
+ - + - +
- ]
874 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true;
# # # # ]
875 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true;
# # # # ]
876 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true;
# # # # ]
877 [ # # # # : 26 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true;
# # # # ]
878 : 0 : }
879 : :
880 [ + + + - : 3295 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL &&
+ - + + -
+ ]
881 [ + + + - : 2163 : ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE &&
+ - + + ]
882 [ + - + - ]: 123 : !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
883 : 125 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES,
884 [ + - + - : 123 : ctrlr->opts.admin_timeout_ms);
+ - ]
885 : :
886 : 2 : } else {
887 : 3985 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
888 [ + - + - : 3170 : ctrlr->opts.admin_timeout_ms);
+ - ]
889 : :
890 : : }
891 : :
892 : 3293 : return rc;
893 : : }
894 : :
895 : : static void
896 : 2163 : nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
897 : : {
898 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
+ - + - ]
899 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
+ - + - ]
900 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
+ - + - ]
901 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
+ - + - ]
902 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
+ - + - ]
903 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
+ - + - ]
904 [ + - + - : 2163 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
+ - + - ]
905 : 2163 : }
906 : :
907 : : static void
908 : 3299 : nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
909 : : {
910 : : uint32_t cdw11;
911 : : struct nvme_completion_poll_status *status;
912 : :
913 [ + + + - : 3299 : if (ctrlr->opts.arbitration_burst == 0) {
+ - - + ]
914 : 3293 : return;
915 : : }
916 : :
917 [ + + # # : 6 : if (ctrlr->opts.arbitration_burst > 7) {
# # # # ]
918 [ + - # # : 3 : NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n");
# # # # #
# # # # #
# # # # #
# ]
919 : 3 : return;
920 : : }
921 : :
922 : 3 : status = calloc(1, sizeof(*status));
923 [ - + ]: 3 : if (!status) {
924 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
925 : 0 : return;
926 : : }
927 : :
928 [ # # # # : 3 : cdw11 = ctrlr->opts.arbitration_burst;
# # ]
929 : :
930 [ + - ]: 3 : if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
931 [ # # # # : 3 : cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
# # # # ]
932 [ # # # # : 3 : cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
# # # # ]
933 [ # # # # : 3 : cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
# # # # ]
934 : 0 : }
935 : :
936 [ - + # # : 3 : if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
# # ]
937 : 0 : cdw11, 0, NULL, 0,
938 : 0 : nvme_completion_poll_cb, status) < 0) {
939 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n");
# # # # #
# # # # #
# # # # #
# ]
940 : 0 : free(status);
941 : 0 : return;
942 : : }
943 : :
944 [ - + # # : 3 : if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
# # ]
945 [ # # # # : 3 : ctrlr->opts.admin_timeout_ms * 1000)) {
# # ]
946 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n");
# # # # #
# # # # #
# # # # #
# ]
947 : 0 : }
948 : :
949 [ + + + - : 3 : if (!status->timed_out) {
# # # # ]
950 : 3 : free(status);
951 : 0 : }
952 : 817 : }
953 : :
954 : : static void
955 : 3293 : nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
956 : : {
957 [ + + + - ]: 3293 : memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
958 : : /* Mandatory features */
959 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
+ - + - ]
960 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
+ - + - ]
961 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
+ - + - ]
962 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
+ - + - ]
963 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
+ - + - ]
964 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
+ - + - ]
965 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
+ - + - ]
966 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
+ - + - ]
967 [ + - + - : 3293 : ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
+ - + - ]
968 : : /* Optional features */
969 [ + + + - : 3293 : if (ctrlr->cdata.vwc.present) {
+ - + + ]
970 [ + - + - : 3103 : ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
+ - + - ]
971 : 815 : }
972 [ + + + - : 3293 : if (ctrlr->cdata.apsta.supported) {
+ - + - ]
973 [ # # # # : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
# # # # ]
974 : 0 : }
975 [ + + + - : 3293 : if (ctrlr->cdata.hmpre) {
+ - + - ]
976 [ # # # # : 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
# # # # ]
977 : 0 : }
978 [ + + + - : 3293 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
+ - + + ]
979 : 2163 : nvme_ctrlr_set_intel_supported_features(ctrlr);
980 : 810 : }
981 : :
982 : 3293 : nvme_ctrlr_set_arbitration_feature(ctrlr);
983 : 3293 : }
984 : :
985 : : static void
986 : 665 : nvme_ctrlr_set_host_feature_done(void *arg, const struct spdk_nvme_cpl *cpl)
987 : : {
988 : 665 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
989 : :
990 [ # # # # ]: 665 : spdk_free(ctrlr->tmp_ptr);
991 [ # # # # ]: 665 : ctrlr->tmp_ptr = NULL;
992 : :
993 [ + - - + : 665 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
994 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set host behavior support feature failed: SC %x SCT %x\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
995 : : cpl->status.sc, cpl->status.sct);
996 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
997 : 0 : return;
998 : : }
999 : :
1000 [ # # # # : 665 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT] = true;
# # # # ]
1001 : :
1002 : 665 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
1003 [ # # # # : 665 : ctrlr->opts.admin_timeout_ms);
# # ]
1004 : 0 : }
1005 : :
1006 : : /* We do not want to do add synchronous operation anymore.
1007 : : * We set the Host Behavior Support feature asynchronousin in different states.
1008 : : */
1009 : : static int
1010 : 3293 : nvme_ctrlr_set_host_feature(struct spdk_nvme_ctrlr *ctrlr)
1011 : : {
1012 : : struct spdk_nvme_host_behavior *host;
1013 : : int rc;
1014 : :
1015 [ + + + - : 3293 : if (!ctrlr->cdata.ctratt.bits.elbas) {
+ - + - -
+ ]
1016 : 3445 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
1017 [ + - + - : 2628 : ctrlr->opts.admin_timeout_ms);
+ - ]
1018 : 2628 : return 0;
1019 : : }
1020 : :
1021 [ # # # # ]: 665 : ctrlr->tmp_ptr = spdk_dma_zmalloc(sizeof(struct spdk_nvme_host_behavior), 4096, NULL);
1022 [ - + # # : 665 : if (!ctrlr->tmp_ptr) {
# # ]
1023 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate host behavior support data\n");
# # # # #
# # # # #
# # # # #
# ]
1024 : 0 : rc = -ENOMEM;
1025 : 0 : goto error;
1026 : : }
1027 : :
1028 : 665 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE,
1029 [ # # # # : 665 : ctrlr->opts.admin_timeout_ms);
# # ]
1030 : :
1031 [ # # # # ]: 665 : host = ctrlr->tmp_ptr;
1032 : :
1033 [ # # # # ]: 665 : host->lbafee = 1;
1034 : :
1035 : 665 : rc = spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT,
1036 : 0 : 0, 0, host, sizeof(struct spdk_nvme_host_behavior),
1037 : 0 : nvme_ctrlr_set_host_feature_done, ctrlr);
1038 [ - + ]: 665 : if (rc != 0) {
1039 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set host behavior support feature failed: %d\n", rc);
# # # # #
# # # # #
# # # # #
# ]
1040 : 0 : goto error;
1041 : : }
1042 : :
1043 : 665 : return 0;
1044 : :
1045 : 0 : error:
1046 [ # # # # ]: 0 : spdk_free(ctrlr->tmp_ptr);
1047 [ # # # # ]: 0 : ctrlr->tmp_ptr = NULL;
1048 : :
1049 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1050 : 0 : return rc;
1051 : 817 : }
1052 : :
1053 : : bool
1054 : 70040 : spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
1055 : : {
1056 [ - + # # : 70040 : return ctrlr->is_failed;
# # ]
1057 : : }
1058 : :
1059 : : void
1060 : 622 : nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
1061 : : {
1062 : : /*
1063 : : * Set the flag here and leave the work failure of qpairs to
1064 : : * spdk_nvme_qpair_process_completions().
1065 : : */
1066 [ + + # # ]: 622 : if (hot_remove) {
1067 [ # # # # ]: 75 : ctrlr->is_removed = true;
1068 : 0 : }
1069 : :
1070 [ - + + + : 622 : if (ctrlr->is_failed) {
# # # # ]
1071 [ + + # # : 53 : NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n");
# # # # #
# # # # #
# # # # #
# ]
1072 : 53 : return;
1073 : : }
1074 : :
1075 [ - + + + : 569 : if (ctrlr->is_disconnecting) {
# # # # ]
1076 [ - + - + : 8 : NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
1077 : 8 : return;
1078 : : }
1079 : :
1080 [ # # # # ]: 561 : ctrlr->is_failed = true;
1081 : 561 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1082 [ # # # # ]: 561 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1083 [ + + # # : 561 : NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n");
# # # # #
# # # # #
# # # # #
# ]
1084 : 0 : }
1085 : :
1086 : : /**
1087 : : * This public API function will try to take the controller lock.
1088 : : * Any private functions being called from a thread already holding
1089 : : * the ctrlr lock should call nvme_ctrlr_fail directly.
1090 : : */
1091 : : void
1092 : 43 : spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
1093 : : {
1094 : 43 : nvme_ctrlr_lock(ctrlr);
1095 : 43 : nvme_ctrlr_fail(ctrlr, false);
1096 : 43 : nvme_ctrlr_unlock(ctrlr);
1097 : 43 : }
1098 : :
1099 : : static void
1100 : 3232 : nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1101 : : {
1102 : 3232 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1103 [ + - + - ]: 3232 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1104 : :
1105 [ + - + + : 3232 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1106 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
# # # # #
# # # # #
# # # # #
# ]
1107 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1108 : 0 : return;
1109 : : }
1110 : :
1111 [ + + + + : 3232 : if (ctrlr->opts.no_shn_notification) {
+ - + - -
+ ]
1112 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1113 : 0 : return;
1114 : : }
1115 : :
1116 : : /*
1117 : : * The NVMe specification defines RTD3E to be the time between
1118 : : * setting SHN = 1 until the controller will set SHST = 10b.
1119 : : * If the device doesn't report RTD3 entry latency, or if it
1120 : : * reports RTD3 entry latency less than 10 seconds, pick
1121 : : * 10 seconds as a reasonable amount of time to
1122 : : * wait before proceeding.
1123 : : */
1124 [ + + + + : 3232 : NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
1125 [ + - + - : 3232 : ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
+ - + - +
- + - ]
1126 [ + - + - : 3232 : ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
- + # # #
# + - +
- ]
1127 [ + + + + : 3232 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms);
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1128 : :
1129 [ + - + - ]: 3232 : ctx->shutdown_start_tsc = spdk_get_ticks();
1130 [ + - + - ]: 3232 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1131 : 817 : }
1132 : :
1133 : : static void
1134 : 3232 : nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1135 : : {
1136 : 3232 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1137 [ + - + - ]: 3232 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1138 : : union spdk_nvme_cc_register cc;
1139 : : int rc;
1140 : :
1141 [ + - + + : 3232 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1142 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# ]
1143 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1144 : 0 : return;
1145 : : }
1146 : :
1147 [ + + # # ]: 3232 : assert(value <= UINT32_MAX);
1148 : 3232 : cc.raw = (uint32_t)value;
1149 : :
1150 [ + + + + : 3232 : if (ctrlr->opts.no_shn_notification) {
+ - + - -
+ ]
1151 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1152 [ # # ]: 0 : if (cc.bits.en == 0) {
1153 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1154 : 0 : return;
1155 : : }
1156 : :
1157 : 0 : cc.bits.en = 0;
1158 : 0 : } else {
1159 : 3232 : cc.bits.shn = SPDK_NVME_SHN_NORMAL;
1160 : : }
1161 : :
1162 : 3232 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx);
1163 [ + + ]: 3232 : if (rc != 0) {
1164 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
# # # # #
# # # # #
# # # # #
# ]
1165 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1166 : 0 : }
1167 : 817 : }
1168 : :
1169 : : static void
1170 : 3462 : nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
1171 : : struct nvme_ctrlr_detach_ctx *ctx)
1172 : : {
1173 : : int rc;
1174 : :
1175 [ + + + + : 3462 : if (ctrlr->is_removed) {
+ - - + ]
1176 [ # # # # ]: 72 : ctx->shutdown_complete = true;
1177 : 72 : return;
1178 : : }
1179 : :
1180 [ + + + - : 4207 : if (ctrlr->adminq == NULL ||
+ - + - ]
1181 [ + + + - : 3369 : ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) {
+ - ]
1182 [ - + - + : 155 : NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
1183 [ # # # # ]: 155 : ctx->shutdown_complete = true;
1184 : 155 : return;
1185 : : }
1186 : :
1187 [ + - + - ]: 3235 : ctx->state = NVME_CTRLR_DETACH_SET_CC;
1188 : 3235 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx);
1189 [ + + ]: 3235 : if (rc != 0) {
1190 [ + - # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# ]
1191 [ # # # # ]: 3 : ctx->shutdown_complete = true;
1192 : 0 : }
1193 : 817 : }
1194 : :
1195 : : static void
1196 : 6273869 : nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1197 : : {
1198 : 6273869 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1199 : :
1200 [ + - + + : 6273869 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1201 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1202 [ # # # # ]: 0 : ctx->shutdown_complete = true;
1203 : 0 : return;
1204 : : }
1205 : :
1206 [ + + # # ]: 6273869 : assert(value <= UINT32_MAX);
1207 [ + - + - : 6273869 : ctx->csts.raw = (uint32_t)value;
+ - ]
1208 [ + - + - ]: 6273869 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE;
1209 : 390065 : }
1210 : :
1211 : : static int
1212 : 20243738 : nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
1213 : : struct nvme_ctrlr_detach_ctx *ctx)
1214 : : {
1215 : : union spdk_nvme_csts_register csts;
1216 : : uint32_t ms_waited;
1217 : :
1218 [ + + + - : 20243738 : switch (ctx->state) {
- + + + ]
1219 : 7281333 : case NVME_CTRLR_DETACH_SET_CC:
1220 : : case NVME_CTRLR_DETACH_GET_CSTS:
1221 : : /* We're still waiting for the register operation to complete */
1222 [ + - + - ]: 7696000 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1223 : 7696000 : return -EAGAIN;
1224 : :
1225 : 5883804 : case NVME_CTRLR_DETACH_CHECK_CSTS:
1226 [ + - + - ]: 6273869 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS;
1227 [ - + ]: 6273869 : if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) {
1228 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# ]
1229 : 0 : return -EIO;
1230 : : }
1231 : 6273869 : return -EAGAIN;
1232 : :
1233 : 5883804 : case NVME_CTRLR_DETACH_GET_CSTS_DONE:
1234 [ + - + - ]: 6273869 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1235 : 6273869 : break;
1236 : :
1237 : 0 : default:
1238 [ # # ]: 0 : assert(0 && "Should never happen");
1239 : : return -EINVAL;
1240 : : }
1241 : :
1242 [ + + + - : 6273869 : ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
+ - ]
1243 [ + - + - : 6273869 : csts.raw = ctx->csts.raw;
+ - ]
1244 : :
1245 [ + + ]: 6273869 : if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
1246 [ + + + + : 3232 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited);
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
1247 : 3232 : return 0;
1248 : : }
1249 : :
1250 [ + - + - : 6270637 : if (ms_waited < ctx->shutdown_timeout_ms) {
+ - ]
1251 : 6270637 : return -EAGAIN;
1252 : : }
1253 : :
1254 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n",
# # # # #
# # # # #
# # # # #
# # # #
# ]
1255 : : ctx->shutdown_timeout_ms);
1256 [ # # # # : 0 : if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
# # ]
1257 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
# # # # #
# # # # #
# # # # #
# ]
1258 : 0 : }
1259 : :
1260 : 0 : return 0;
1261 : 1194797 : }
1262 : :
1263 : : static inline uint64_t
1264 : 5847254 : nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr)
1265 : : {
1266 [ + - + - : 5847254 : return ctrlr->cap.bits.to * 500;
+ - + - ]
1267 : : }
1268 : :
1269 : : static void
1270 : 3439 : nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1271 : : {
1272 : 3439 : struct spdk_nvme_ctrlr *ctrlr = ctx;
1273 : :
1274 [ + - + + : 3439 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
1275 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n");
# # # # #
# # # # #
# # # # #
# ]
1276 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1277 : 0 : return;
1278 : : }
1279 : :
1280 : 4256 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
1281 : 817 : nvme_ctrlr_get_ready_timeout(ctrlr));
1282 : 817 : }
1283 : :
1284 : : static int
1285 : 3460 : nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
1286 : : {
1287 : : union spdk_nvme_cc_register cc;
1288 : : int rc;
1289 : :
1290 : 3460 : rc = nvme_transport_ctrlr_enable(ctrlr);
1291 [ - + ]: 3460 : if (rc != 0) {
1292 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n");
# # # # #
# # # # #
# # # # #
# ]
1293 : 0 : return rc;
1294 : : }
1295 : :
1296 [ + - + - : 3460 : cc.raw = ctrlr->process_init_cc.raw;
+ - ]
1297 [ - + ]: 3460 : if (cc.bits.en != 0) {
1298 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n");
# # # # #
# # # # #
# # # # #
# ]
1299 : 0 : return -EINVAL;
1300 : : }
1301 : :
1302 : 3460 : cc.bits.en = 1;
1303 : 3460 : cc.bits.css = 0;
1304 : 3460 : cc.bits.shn = 0;
1305 : 3460 : cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1306 : 3460 : cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1307 : :
1308 : : /* Page size is 2 ^ (12 + mps). */
1309 [ + - + - ]: 3460 : cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1310 : :
1311 : : /*
1312 : : * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1313 : : * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1314 : : * Try to support such a controller regardless.
1315 : : */
1316 [ + + + - : 3460 : if (ctrlr->cap.bits.css == 0) {
+ - + - ]
1317 [ - + - + : 63 : NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
1318 [ # # # # : 63 : ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
# # # # ]
1319 : 0 : }
1320 : :
1321 : : /*
1322 : : * If the user did not explicitly request a command set, or supplied a value larger than
1323 : : * what can be saved in CC.CSS, use the most reasonable default.
1324 : : */
1325 [ + + + - : 3460 : if (ctrlr->opts.command_set >= CHAR_BIT) {
+ - - + ]
1326 [ + + + - : 3269 : if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
+ - + - -
+ ]
1327 [ # # # # : 919 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
# # ]
1328 [ + - + - : 2350 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
+ - + - +
- ]
1329 [ + - + - : 2350 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
+ - ]
1330 [ # # # # : 817 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
# # # # #
# ]
1331 : : /* Technically we should respond with CC_CSS_NOIO in
1332 : : * this case, but we use NVM instead to work around
1333 : : * buggy targets and to match Linux driver behavior.
1334 : : */
1335 [ # # # # : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
# # ]
1336 : 0 : } else {
1337 : : /* Invalid supported bits detected, falling back to NVM. */
1338 [ # # # # : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
# # ]
1339 : : }
1340 : 817 : }
1341 : :
1342 : : /* Verify that the selected command set is supported by the controller. */
1343 [ + + + + : 3460 : if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
+ - + - +
- + - + -
+ - ]
1344 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
1345 : : ctrlr->opts.command_set, ctrlr->cap.bits.css);
1346 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
1347 [ # # # # : 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
# # ]
1348 : 0 : }
1349 : :
1350 [ + - + - : 3460 : cc.bits.css = ctrlr->opts.command_set;
+ - ]
1351 : :
1352 [ + + + + : 3460 : switch (ctrlr->opts.arb_mechanism) {
+ - - + -
- ]
1353 : 2610 : case SPDK_NVME_CC_AMS_RR:
1354 : 3427 : break;
1355 : 12 : case SPDK_NVME_CC_AMS_WRR:
1356 [ + + # # : 12 : if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
# # # # ]
1357 : 6 : break;
1358 : : }
1359 : 6 : return -EINVAL;
1360 : 12 : case SPDK_NVME_CC_AMS_VS:
1361 [ + + # # : 12 : if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
# # # # ]
1362 : 6 : break;
1363 : : }
1364 : 6 : return -EINVAL;
1365 : 9 : default:
1366 : 9 : return -EINVAL;
1367 : : }
1368 : :
1369 [ + - + - : 3439 : cc.bits.ams = ctrlr->opts.arb_mechanism;
+ - ]
1370 [ + - + - : 3439 : ctrlr->process_init_cc.raw = cc.raw;
+ - ]
1371 : :
1372 [ - + ]: 3439 : if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) {
1373 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
# # # # #
# # # # #
# # # # #
# ]
1374 : 0 : return -EIO;
1375 : : }
1376 : :
1377 : 3439 : return 0;
1378 : 817 : }
1379 : :
1380 : : static const char *
1381 : 383 : nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1382 : : {
1383 [ - + + + : 383 : switch (state) {
+ + + + +
- - - - +
- + + + +
- + + + +
+ + + + -
- - + + +
+ + + + +
+ - + - -
+ + - + -
+ - + + +
- - ]
1384 : 0 : case NVME_CTRLR_STATE_INIT_DELAY:
1385 : 0 : return "delay init";
1386 : 12 : case NVME_CTRLR_STATE_CONNECT_ADMINQ:
1387 : 12 : return "connect adminq";
1388 : 12 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
1389 : 12 : return "wait for connect adminq";
1390 : 12 : case NVME_CTRLR_STATE_READ_VS:
1391 : 12 : return "read vs";
1392 : 12 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
1393 : 12 : return "read vs wait for vs";
1394 : 12 : case NVME_CTRLR_STATE_READ_CAP:
1395 : 12 : return "read cap";
1396 : 12 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
1397 : 12 : return "read cap wait for cap";
1398 : 12 : case NVME_CTRLR_STATE_CHECK_EN:
1399 : 12 : return "check en";
1400 : 12 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
1401 : 12 : return "check en wait for cc";
1402 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1403 : 0 : return "disable and wait for CSTS.RDY = 1";
1404 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1405 : 0 : return "disable and wait for CSTS.RDY = 1 reg";
1406 : 0 : case NVME_CTRLR_STATE_SET_EN_0:
1407 : 0 : return "set CC.EN = 0";
1408 : 0 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
1409 : 0 : return "set CC.EN = 0 wait for cc";
1410 : 12 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1411 : 12 : return "disable and wait for CSTS.RDY = 0";
1412 : 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
1413 : 0 : return "disable and wait for CSTS.RDY = 0 reg";
1414 : 12 : case NVME_CTRLR_STATE_DISABLED:
1415 : 12 : return "controller is disabled";
1416 : 12 : case NVME_CTRLR_STATE_ENABLE:
1417 : 12 : return "enable controller by writing CC.EN = 1";
1418 : 12 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
1419 : 12 : return "enable controller by writing CC.EN = 1 reg";
1420 : 12 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1421 : 12 : return "wait for CSTS.RDY = 1";
1422 : 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1423 : 0 : return "wait for CSTS.RDY = 1 reg";
1424 : 12 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1425 : 12 : return "reset admin queue";
1426 : 12 : case NVME_CTRLR_STATE_IDENTIFY:
1427 : 12 : return "identify controller";
1428 : 12 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1429 : 12 : return "wait for identify controller";
1430 : 12 : case NVME_CTRLR_STATE_CONFIGURE_AER:
1431 : 12 : return "configure AER";
1432 : 12 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1433 : 12 : return "wait for configure aer";
1434 : 12 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1435 : 12 : return "set keep alive timeout";
1436 : 12 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1437 : 12 : return "wait for set keep alive timeout";
1438 : 8 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1439 : 8 : return "identify controller iocs specific";
1440 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1441 : 0 : return "wait for identify controller iocs specific";
1442 : 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1443 : 0 : return "get zns cmd and effects log page";
1444 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1445 : 0 : return "wait for get zns cmd and effects log page";
1446 : 8 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1447 : 8 : return "set number of queues";
1448 : 8 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1449 : 8 : return "wait for set number of queues";
1450 : 8 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1451 : 8 : return "identify active ns";
1452 : 8 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1453 : 8 : return "wait for identify active ns";
1454 : 8 : case NVME_CTRLR_STATE_IDENTIFY_NS:
1455 : 8 : return "identify ns";
1456 : 8 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1457 : 8 : return "wait for identify ns";
1458 : 8 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1459 : 8 : return "identify namespace id descriptors";
1460 : 8 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1461 : 8 : return "wait for identify namespace id descriptors";
1462 : 8 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1463 : 8 : return "identify ns iocs specific";
1464 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1465 : 0 : return "wait for identify ns iocs specific";
1466 : 8 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1467 : 8 : return "set supported log pages";
1468 : 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
1469 : 0 : return "set supported INTEL log pages";
1470 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
1471 : 0 : return "wait for supported INTEL log pages";
1472 : 8 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1473 : 8 : return "set supported features";
1474 : 8 : case NVME_CTRLR_STATE_SET_HOST_FEATURE:
1475 : 8 : return "set host behavior support feature";
1476 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE:
1477 : 0 : return "wait for set host behavior support feature";
1478 : 8 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1479 : 8 : return "set doorbell buffer config";
1480 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1481 : 0 : return "wait for doorbell buffer config";
1482 : 8 : case NVME_CTRLR_STATE_SET_HOST_ID:
1483 : 8 : return "set host ID";
1484 : 0 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1485 : 0 : return "wait for set host ID";
1486 : 8 : case NVME_CTRLR_STATE_TRANSPORT_READY:
1487 : 8 : return "transport ready";
1488 : 12 : case NVME_CTRLR_STATE_READY:
1489 : 12 : return "ready";
1490 : 3 : case NVME_CTRLR_STATE_ERROR:
1491 : 3 : return "error";
1492 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
1493 : 0 : return "disconnected";
1494 : : }
1495 : 0 : return "unknown";
1496 : 0 : };
1497 : :
1498 : : static void
1499 : 207503 : _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1500 : : uint64_t timeout_in_ms, bool quiet)
1501 : : {
1502 : : uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1503 : :
1504 [ + - + - ]: 207503 : ctrlr->state = state;
1505 [ + + ]: 207503 : if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
1506 [ + + + - ]: 72247 : if (!quiet) {
1507 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1508 : : nvme_ctrlr_state_string(ctrlr->state));
1509 : 0 : }
1510 : 72247 : return;
1511 : : }
1512 : :
1513 [ + + ]: 135256 : if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1514 : 35822 : goto inf;
1515 : : }
1516 : :
1517 [ + - ]: 99434 : ticks_per_ms = spdk_get_ticks_hz() / 1000;
1518 [ + + - + ]: 99434 : if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1519 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr,
# # # # #
# # # # #
# # # # #
# ]
1520 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1521 : 0 : goto inf;
1522 : : }
1523 : :
1524 : 99434 : now_ticks = spdk_get_ticks();
1525 : 99434 : timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1526 [ + + ]: 99434 : if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1527 [ + - # # : 3 : NVME_CTRLR_ERRLOG(ctrlr,
# # # # #
# # # # #
# # # # #
# ]
1528 : : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1529 : 3 : goto inf;
1530 : : }
1531 : :
1532 [ + - + - ]: 99431 : ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1533 [ + - - + ]: 99431 : if (!quiet) {
1534 [ + + + + : 99431 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1535 : : nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1536 : 22876 : }
1537 : 99431 : return;
1538 : 28470 : inf:
1539 [ + - - + ]: 35825 : if (!quiet) {
1540 [ + + + + : 35825 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1541 : : nvme_ctrlr_state_string(ctrlr->state));
1542 : 7355 : }
1543 [ + - + - ]: 35825 : ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1544 : 37839 : }
1545 : :
1546 : : static void
1547 : 135256 : nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1548 : : uint64_t timeout_in_ms)
1549 : : {
1550 : 135256 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
1551 : 135256 : }
1552 : :
1553 : : static void
1554 : 72247 : nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1555 : : uint64_t timeout_in_ms)
1556 : : {
1557 : 72247 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
1558 : 72247 : }
1559 : :
1560 : : static void
1561 : 3976 : nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1562 : : {
1563 [ + - + - ]: 3976 : spdk_free(ctrlr->cdata_zns);
1564 [ + - + - ]: 3976 : ctrlr->cdata_zns = NULL;
1565 : 3976 : }
1566 : :
1567 : : static void
1568 : 3976 : nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1569 : : {
1570 : 3976 : nvme_ctrlr_free_zns_specific_data(ctrlr);
1571 : 3976 : }
1572 : :
1573 : : static void
1574 : 3979 : nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1575 : : {
1576 [ + + + - : 3979 : if (ctrlr->shadow_doorbell) {
- + ]
1577 [ # # # # ]: 661 : spdk_free(ctrlr->shadow_doorbell);
1578 [ # # # # ]: 661 : ctrlr->shadow_doorbell = NULL;
1579 : 0 : }
1580 : :
1581 [ + + + - : 3979 : if (ctrlr->eventidx) {
- + ]
1582 [ # # # # ]: 661 : spdk_free(ctrlr->eventidx);
1583 [ # # # # ]: 661 : ctrlr->eventidx = NULL;
1584 : 0 : }
1585 : 3979 : }
1586 : :
1587 : : static void
1588 : 665 : nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1589 : : {
1590 : 665 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1591 : :
1592 [ + - - + : 665 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
1593 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n");
# # # # #
# # # # #
# # # # #
# ]
1594 : 0 : } else {
1595 [ - + - + : 665 : NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
1596 : : }
1597 : 665 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1598 [ # # # # : 665 : ctrlr->opts.admin_timeout_ms);
# # ]
1599 : 665 : }
1600 : :
1601 : : static int
1602 : 3290 : nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1603 : : {
1604 : 3290 : int rc = 0;
1605 : 485 : uint64_t prp1, prp2, len;
1606 : :
1607 [ + + + - : 3290 : if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
+ - - + ]
1608 : 3442 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1609 [ + - + - : 2625 : ctrlr->opts.admin_timeout_ms);
+ - ]
1610 : 2625 : return 0;
1611 : : }
1612 : :
1613 [ - + # # : 665 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
# # # # ]
1614 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1615 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
1616 : 0 : return 0;
1617 : : }
1618 : :
1619 : : /* only 1 page size for doorbell buffer */
1620 [ # # # # : 665 : ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
# # # # #
# # # ]
1621 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1622 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1623 [ - + # # : 665 : if (ctrlr->shadow_doorbell == NULL) {
# # ]
1624 : 0 : rc = -ENOMEM;
1625 : 0 : goto error;
1626 : : }
1627 : :
1628 [ # # # # ]: 665 : len = ctrlr->page_size;
1629 [ # # # # ]: 665 : prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1630 [ + - - + : 665 : if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
# # # # ]
1631 : 0 : rc = -EFAULT;
1632 : 0 : goto error;
1633 : : }
1634 : :
1635 [ # # # # : 665 : ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
# # # # #
# # # ]
1636 : : NULL, SPDK_ENV_LCORE_ID_ANY,
1637 : : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1638 [ - + # # : 665 : if (ctrlr->eventidx == NULL) {
# # ]
1639 : 0 : rc = -ENOMEM;
1640 : 0 : goto error;
1641 : : }
1642 : :
1643 [ # # # # ]: 665 : len = ctrlr->page_size;
1644 [ # # # # ]: 665 : prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1645 [ + - - + : 665 : if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
# # # # ]
1646 : 0 : rc = -EFAULT;
1647 : 0 : goto error;
1648 : : }
1649 : :
1650 : 665 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1651 [ # # # # : 665 : ctrlr->opts.admin_timeout_ms);
# # ]
1652 : :
1653 : 665 : rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1654 : 0 : nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1655 [ - + ]: 665 : if (rc != 0) {
1656 : 0 : goto error;
1657 : : }
1658 : :
1659 : 665 : return 0;
1660 : :
1661 : 0 : error:
1662 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1663 : 0 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1664 : 0 : return rc;
1665 : 817 : }
1666 : :
1667 : : void
1668 : 6570 : nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1669 : : {
1670 : : struct nvme_request *req, *tmp;
1671 : 6570 : struct spdk_nvme_cpl cpl = {};
1672 : :
1673 [ + - + - ]: 6570 : cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1674 [ + - + - ]: 6570 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1675 : :
1676 [ + + + - : 6570 : STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
+ - + - #
# # # # #
+ - ]
1677 [ # # # # : 0 : STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
1678 [ # # ]: 0 : ctrlr->outstanding_aborts++;
1679 : :
1680 [ # # # # : 0 : nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
# # # # #
# # # ]
1681 : 0 : }
1682 : 6570 : }
1683 : :
1684 : : static int
1685 : 517 : nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1686 : : {
1687 [ + + + + : 517 : if (ctrlr->is_resetting || ctrlr->is_removed) {
- + - + #
# # # # #
# # ]
1688 : : /*
1689 : : * Controller is already resetting or has been removed. Return
1690 : : * immediately since there is no need to kick off another
1691 : : * reset in these cases.
1692 : : */
1693 [ + + + - : 3 : return ctrlr->is_resetting ? -EBUSY : -ENXIO;
# # ]
1694 : : }
1695 : :
1696 [ # # # # ]: 514 : ctrlr->is_resetting = true;
1697 [ # # # # ]: 514 : ctrlr->is_failed = false;
1698 [ # # # # ]: 514 : ctrlr->is_disconnecting = true;
1699 [ # # # # ]: 514 : ctrlr->prepare_for_reset = true;
1700 : :
1701 [ + + # # : 514 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n");
# # # # #
# # # # #
# # # # #
# ]
1702 : :
1703 : : /* Disable keep-alive, it'll be re-enabled as part of the init process */
1704 [ # # # # ]: 514 : ctrlr->keep_alive_interval_ticks = 0;
1705 : :
1706 : : /* Abort all of the queued abort requests */
1707 : 514 : nvme_ctrlr_abort_queued_aborts(ctrlr);
1708 : :
1709 [ # # # # ]: 514 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1710 : :
1711 [ # # # # : 514 : ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
# # ]
1712 [ # # # # ]: 514 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1713 : :
1714 : 514 : return 0;
1715 : 0 : }
1716 : :
1717 : : static void
1718 : 514 : nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr)
1719 : : {
1720 [ - + - + : 514 : assert(ctrlr->is_failed == false);
# # # # #
# ]
1721 [ # # # # ]: 514 : ctrlr->is_disconnecting = false;
1722 : :
1723 : : /* Doorbell buffer config is invalid during reset */
1724 : 514 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1725 : :
1726 : : /* I/O Command Set Specific Identify Controller data is invalidated during reset */
1727 : 514 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
1728 : :
1729 [ # # ]: 514 : spdk_bit_array_free(&ctrlr->free_io_qids);
1730 : :
1731 : : /* Set the state back to DISCONNECTED to cause a full hardware reset. */
1732 : 514 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE);
1733 : 514 : }
1734 : :
1735 : : int
1736 : 459 : spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1737 : : {
1738 : : int rc;
1739 : :
1740 : 459 : nvme_ctrlr_lock(ctrlr);
1741 : 459 : rc = nvme_ctrlr_disconnect(ctrlr);
1742 : 459 : nvme_ctrlr_unlock(ctrlr);
1743 : :
1744 : 459 : return rc;
1745 : : }
1746 : :
1747 : : void
1748 : 514 : spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr)
1749 : : {
1750 : 514 : nvme_ctrlr_lock(ctrlr);
1751 : :
1752 [ # # # # ]: 514 : ctrlr->prepare_for_reset = false;
1753 : :
1754 : : /* Set the state back to INIT to cause a full hardware reset. */
1755 : 514 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1756 : :
1757 : : /* Return without releasing ctrlr_lock. ctrlr_lock will be released when
1758 : : * spdk_nvme_ctrlr_reset_poll_async() returns 0.
1759 : : */
1760 : 514 : }
1761 : :
1762 : : int
1763 : 29 : nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1764 : : {
1765 : : bool async;
1766 : : int rc;
1767 : :
1768 [ + - + - : 58 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc ||
# # ]
1769 [ - + ]: 58 : spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) {
1770 [ # # ]: 0 : assert(false);
1771 : : return -EINVAL;
1772 : : }
1773 : :
1774 : : /* Force a synchronous connect. */
1775 [ # # ]: 29 : async = qpair->async;
1776 [ # # ]: 29 : qpair->async = false;
1777 : 29 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1778 [ # # # # ]: 29 : qpair->async = async;
1779 : :
1780 [ - + ]: 29 : if (rc != 0) {
1781 [ # # ]: 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1782 : 0 : }
1783 : :
1784 : 29 : return rc;
1785 : : }
1786 : :
1787 : : /**
1788 : : * This function will be called when the controller is being reinitialized.
1789 : : * Note: the ctrlr_lock must be held when calling this function.
1790 : : */
1791 : : int
1792 : 723705 : spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr)
1793 : : {
1794 : : struct spdk_nvme_ns *ns, *tmp_ns;
1795 : : struct spdk_nvme_qpair *qpair;
1796 : 723705 : int rc = 0, rc_tmp = 0;
1797 : :
1798 [ + + ]: 723705 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1799 [ + - # # : 383 : NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n");
# # # # #
# # # # #
# # # # #
# ]
1800 : 383 : rc = -1;
1801 : 0 : }
1802 [ + + + + : 723705 : if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) {
# # # # ]
1803 : 723191 : return -EAGAIN;
1804 : : }
1805 : :
1806 : : /*
1807 : : * For non-fabrics controllers, the memory locations of the transport qpair
1808 : : * don't change when the controller is reset. They simply need to be
1809 : : * re-enabled with admin commands to the controller. For fabric
1810 : : * controllers we need to disconnect and reconnect the qpair on its
1811 : : * own thread outside of the context of the reset.
1812 : : */
1813 [ + + + + ]: 514 : if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
1814 : : /* Reinitialize qpairs */
1815 [ + + # # : 118 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
# # # # #
# # # #
# ]
1816 : : /* Always clear the qid bit here, even for a foreign qpair. We need
1817 : : * to make sure another process doesn't get the chance to grab that
1818 : : * qid.
1819 : : */
1820 [ - + # # : 29 : assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
# # # # #
# # # ]
1821 [ # # # # : 29 : spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
# # # # ]
1822 [ + + # # : 29 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) {
# # ]
1823 : : /*
1824 : : * We cannot reinitialize a foreign qpair. The qpair's owning
1825 : : * process will take care of it. Set failure reason to FAILURE_RESET
1826 : : * to ensure that happens.
1827 : : */
1828 [ # # ]: 23 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET;
1829 : 23 : continue;
1830 : : }
1831 : 6 : rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair);
1832 [ - + ]: 6 : if (rc_tmp != 0) {
1833 : 0 : rc = rc_tmp;
1834 : 0 : }
1835 : 0 : }
1836 : 0 : }
1837 : :
1838 : : /*
1839 : : * Take this opportunity to remove inactive namespaces. During a reset namespace
1840 : : * handles can be invalidated.
1841 : : */
1842 [ + + + - : 1091 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
# # ]
1843 [ + + + + : 577 : if (!ns->active) {
# # # # ]
1844 [ # # ]: 4 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
1845 : 4 : spdk_free(ns);
1846 : 0 : }
1847 : 0 : }
1848 : :
1849 [ + + ]: 514 : if (rc) {
1850 : 383 : nvme_ctrlr_fail(ctrlr, false);
1851 : 0 : }
1852 [ # # # # ]: 514 : ctrlr->is_resetting = false;
1853 : :
1854 : 514 : nvme_ctrlr_unlock(ctrlr);
1855 : :
1856 [ + + # # : 514 : if (!ctrlr->cdata.oaes.ns_attribute_notices) {
# # # # ]
1857 : : /*
1858 : : * If controller doesn't support ns_attribute_notices and
1859 : : * namespace attributes change (e.g. number of namespaces)
1860 : : * we need to update system handling device reset.
1861 : : */
1862 : 15 : nvme_io_msg_ctrlr_update(ctrlr);
1863 : 0 : }
1864 : :
1865 : 514 : return rc;
1866 : 0 : }
1867 : :
1868 : : /*
1869 : : * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset
1870 : : * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair.
1871 : : * The following two functions are added to do a Controller Level Reset. They have
1872 : : * to be called under the nvme controller's lock.
1873 : : */
1874 : : void
1875 : 89 : nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1876 : : {
1877 [ - + - + : 89 : assert(ctrlr->is_disconnecting == true);
# # # # #
# ]
1878 : :
1879 : 89 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
1880 : 89 : }
1881 : :
1882 : : int
1883 : 1243 : nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr)
1884 : : {
1885 : 1243 : int rc = 0;
1886 : :
1887 [ - + ]: 1243 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1888 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n");
# # # # #
# # # # #
# # # # #
# ]
1889 : 0 : rc = -1;
1890 : 0 : }
1891 : :
1892 [ + + + - : 1243 : if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) {
# # # # ]
1893 : 1154 : return -EAGAIN;
1894 : : }
1895 : :
1896 : 89 : return rc;
1897 : 0 : }
1898 : :
1899 : : static void
1900 : 55 : nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1901 : : {
1902 : : struct spdk_nvme_qpair *qpair;
1903 : :
1904 [ + + # # : 95 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
# # # # #
# # # #
# ]
1905 [ # # ]: 40 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1906 : 0 : }
1907 : 55 : }
1908 : :
1909 : : int
1910 : 58 : spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1911 : : {
1912 : : int rc;
1913 : :
1914 : 58 : nvme_ctrlr_lock(ctrlr);
1915 : :
1916 : 58 : rc = nvme_ctrlr_disconnect(ctrlr);
1917 [ + + ]: 58 : if (rc == 0) {
1918 : 55 : nvme_ctrlr_fail_io_qpairs(ctrlr);
1919 : 0 : }
1920 : :
1921 : 58 : nvme_ctrlr_unlock(ctrlr);
1922 : :
1923 [ + + ]: 58 : if (rc != 0) {
1924 [ + - ]: 3 : if (rc == -EBUSY) {
1925 : 3 : rc = 0;
1926 : 0 : }
1927 : 3 : return rc;
1928 : : }
1929 : :
1930 : 0 : while (1) {
1931 : 384 : rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr);
1932 [ + + ]: 384 : if (rc == -ENXIO) {
1933 : 55 : break;
1934 : : }
1935 : : }
1936 : :
1937 : 55 : spdk_nvme_ctrlr_reconnect_async(ctrlr);
1938 : :
1939 : 0 : while (true) {
1940 : 42234 : rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr);
1941 [ + + ]: 42234 : if (rc != -EAGAIN) {
1942 : 55 : break;
1943 : : }
1944 : : }
1945 : :
1946 : 55 : return rc;
1947 : 0 : }
1948 : :
1949 : : int
1950 : 0 : spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1951 : : {
1952 : : union spdk_nvme_cap_register cap;
1953 : 0 : int rc = 0;
1954 : :
1955 : 0 : cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1956 [ # # ]: 0 : if (cap.bits.nssrs == 0) {
1957 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n");
# # # # #
# # # # #
# # # # #
# ]
1958 : 0 : return -ENOTSUP;
1959 : : }
1960 : :
1961 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n");
# # # # #
# # # # #
# # # # #
# ]
1962 : 0 : nvme_ctrlr_lock(ctrlr);
1963 [ # # # # ]: 0 : ctrlr->is_resetting = true;
1964 : 0 : rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1965 [ # # # # ]: 0 : ctrlr->is_resetting = false;
1966 : :
1967 : 0 : nvme_ctrlr_unlock(ctrlr);
1968 : : /*
1969 : : * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1970 : : * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1971 : : */
1972 : 0 : return rc;
1973 : 0 : }
1974 : :
1975 : : int
1976 : 29 : spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
1977 : : {
1978 : 29 : int rc = 0;
1979 : :
1980 : 29 : nvme_ctrlr_lock(ctrlr);
1981 : :
1982 [ + + + + : 29 : if (ctrlr->is_failed == false) {
# # # # ]
1983 : 3 : rc = -EPERM;
1984 : 3 : goto out;
1985 : : }
1986 : :
1987 [ + + # # : 26 : if (trid->trtype != ctrlr->trid.trtype) {
# # # # #
# # # ]
1988 : 3 : rc = -EINVAL;
1989 : 3 : goto out;
1990 : : }
1991 : :
1992 [ + + - + : 23 : if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
+ + # # #
# # # ]
1993 : 3 : rc = -EINVAL;
1994 : 3 : goto out;
1995 : : }
1996 : :
1997 [ # # ]: 20 : ctrlr->trid = *trid;
1998 : :
1999 : 29 : out:
2000 : 29 : nvme_ctrlr_unlock(ctrlr);
2001 : 29 : return rc;
2002 : : }
2003 : :
2004 : : void
2005 : 1534 : spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
2006 : : spdk_nvme_remove_cb remove_cb, void *remove_ctx)
2007 : : {
2008 [ - + ]: 1534 : if (!spdk_process_is_primary()) {
2009 : 0 : return;
2010 : : }
2011 : :
2012 : 1534 : nvme_ctrlr_lock(ctrlr);
2013 [ - + - + ]: 1534 : ctrlr->remove_cb = remove_cb;
2014 [ - + - + ]: 1534 : ctrlr->cb_ctx = remove_ctx;
2015 : 1534 : nvme_ctrlr_unlock(ctrlr);
2016 : 1 : }
2017 : :
2018 : : int
2019 : 28 : spdk_nvme_ctrlr_set_keys(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ctrlr_key_opts *opts)
2020 : : {
2021 : 28 : nvme_ctrlr_lock(ctrlr);
2022 [ + - + + : 32 : if (SPDK_GET_FIELD(opts, dhchap_key, ctrlr->opts.dhchap_key) == NULL &&
- + # # #
# # # # #
# # # # #
# ]
2023 [ + - # # : 4 : SPDK_GET_FIELD(opts, dhchap_ctrlr_key, ctrlr->opts.dhchap_ctrlr_key) != NULL) {
# # # # #
# # # # #
# # ]
2024 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "DH-HMAC-CHAP controller key requires host key to be set\n");
# # # # #
# # # # #
# # # # #
# ]
2025 : 0 : nvme_ctrlr_unlock(ctrlr);
2026 : 0 : return -EINVAL;
2027 : : }
2028 : :
2029 [ # # # # : 28 : ctrlr->opts.dhchap_key =
# # ]
2030 [ + - # # : 28 : SPDK_GET_FIELD(opts, dhchap_key, ctrlr->opts.dhchap_key);
# # # # #
# # # # #
# # ]
2031 [ # # # # : 28 : ctrlr->opts.dhchap_ctrlr_key =
# # ]
2032 [ + - # # : 28 : SPDK_GET_FIELD(opts, dhchap_ctrlr_key, ctrlr->opts.dhchap_ctrlr_key);
# # # # #
# # # # #
# # ]
2033 : 28 : nvme_ctrlr_unlock(ctrlr);
2034 : :
2035 : 28 : return 0;
2036 : 0 : }
2037 : :
2038 : : static void
2039 : 3445 : nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
2040 : : {
2041 : 3445 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2042 : :
2043 [ + - + + : 3445 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2044 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n");
# # # # #
# # # # #
# # # # #
# ]
2045 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2046 : 0 : return;
2047 : : }
2048 : :
2049 : : /*
2050 : : * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
2051 : : * controller supports.
2052 : : */
2053 [ + - + - ]: 3445 : ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
2054 [ + + + + : 3445 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2055 [ + + + - : 3445 : if (ctrlr->cdata.mdts > 0) {
+ - - + ]
2056 [ + + + + : 3147 : ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
+ + + - +
- + - + -
- + + - -
+ # # # #
+ - + - +
- + - + -
- + + - +
- + - ]
2057 : : ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
2058 [ + + + + : 3147 : NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2059 : 817 : }
2060 : :
2061 [ + + + + : 3445 : NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
2062 [ + + + - : 3445 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
+ - + + ]
2063 [ + - + - : 807 : ctrlr->cntlid = ctrlr->cdata.cntlid;
+ - + - +
- ]
2064 : 2 : } else {
2065 : : /*
2066 : : * Fabrics controllers should already have CNTLID from the Connect command.
2067 : : *
2068 : : * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
2069 : : * trust the one from Connect.
2070 : : */
2071 [ + + + - : 2638 : if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
+ - + - +
- + + ]
2072 [ + + + + : 76 : NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2073 : : ctrlr->cdata.cntlid, ctrlr->cntlid);
2074 : 7 : }
2075 : : }
2076 : :
2077 [ + + + - : 3445 : if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
+ - + + +
- + - -
+ ]
2078 [ + + + - : 3256 : assert(ctrlr->cdata.sgls.supported != 0x3);
+ - + - #
# ]
2079 [ + - + - ]: 3256 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
2080 [ + + + - : 3256 : if (ctrlr->cdata.sgls.supported == 0x2) {
+ - + + ]
2081 [ + - + - ]: 77 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
2082 : 7 : }
2083 : :
2084 [ + - + - ]: 3256 : ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
2085 [ + + + + : 3256 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges);
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2086 : 815 : }
2087 : :
2088 [ + + + - : 3445 : if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
+ - - + #
# # # #
# ]
2089 [ # # # # ]: 1 : ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED;
2090 : 0 : }
2091 : :
2092 [ + + + - : 3445 : if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
+ - - + #
# # # #
# ]
2093 [ # # # # ]: 44 : ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
2094 : 0 : }
2095 : :
2096 [ + + + - : 3445 : if (ctrlr->cdata.oacs.directives) {
+ - + - ]
2097 [ # # # # ]: 663 : ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
2098 : 0 : }
2099 : :
2100 [ + + + + : 3445 : NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n",
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
2101 : : ctrlr->cdata.fuses.compare_and_write);
2102 [ + + + - : 3445 : if (ctrlr->cdata.fuses.compare_and_write) {
+ - + + ]
2103 [ + - + - ]: 2264 : ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
2104 : 815 : }
2105 : :
2106 : 4262 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2107 [ + - + - : 3445 : ctrlr->opts.admin_timeout_ms);
+ - ]
2108 : 817 : }
2109 : :
2110 : : static int
2111 : 3445 : nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
2112 : : {
2113 : : int rc;
2114 : :
2115 : 4262 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
2116 [ + - + - : 3445 : ctrlr->opts.admin_timeout_ms);
+ - ]
2117 : :
2118 : 3445 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
2119 [ + - ]: 3445 : &ctrlr->cdata, sizeof(ctrlr->cdata),
2120 : 817 : nvme_ctrlr_identify_done, ctrlr);
2121 [ - + ]: 3445 : if (rc != 0) {
2122 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2123 : 0 : return rc;
2124 : : }
2125 : :
2126 : 3445 : return 0;
2127 : 817 : }
2128 : :
2129 : : static void
2130 : 987 : nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
2131 : : {
2132 : : struct spdk_nvme_cmds_and_effect_log_page *log_page;
2133 : 987 : struct spdk_nvme_ctrlr *ctrlr = arg;
2134 : :
2135 [ + - - + : 987 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2136 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
# # # # #
# # # # #
# # # # #
# ]
2137 [ # # # # ]: 0 : spdk_free(ctrlr->tmp_ptr);
2138 [ # # # # ]: 0 : ctrlr->tmp_ptr = NULL;
2139 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2140 : 0 : return;
2141 : : }
2142 : :
2143 [ # # # # ]: 987 : log_page = ctrlr->tmp_ptr;
2144 : :
2145 [ + - # # : 987 : if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
# # # # #
# ]
2146 [ # # # # ]: 987 : ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
2147 : 0 : }
2148 [ # # # # ]: 987 : spdk_free(ctrlr->tmp_ptr);
2149 [ # # # # ]: 987 : ctrlr->tmp_ptr = NULL;
2150 : :
2151 [ # # # # : 987 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
# # ]
2152 : 0 : }
2153 : :
2154 : : static int
2155 : 987 : nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
2156 : : {
2157 : : int rc;
2158 : :
2159 [ - + # # : 987 : assert(!ctrlr->tmp_ptr);
# # # # ]
2160 [ # # # # ]: 987 : ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
2161 : : SPDK_ENV_NUMA_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2162 [ - + # # : 987 : if (!ctrlr->tmp_ptr) {
# # ]
2163 : 0 : rc = -ENOMEM;
2164 : 0 : goto error;
2165 : : }
2166 : :
2167 : 987 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
2168 [ # # # # : 987 : ctrlr->opts.admin_timeout_ms);
# # ]
2169 : :
2170 : 987 : rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
2171 [ # # # # ]: 0 : 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
2172 [ # # # # ]: 0 : 0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
2173 : 0 : nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
2174 [ - + ]: 987 : if (rc != 0) {
2175 : 0 : goto error;
2176 : : }
2177 : :
2178 : 987 : return 0;
2179 : :
2180 : 0 : error:
2181 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2182 [ # # # # ]: 0 : spdk_free(ctrlr->tmp_ptr);
2183 [ # # # # ]: 0 : ctrlr->tmp_ptr = NULL;
2184 : 0 : return rc;
2185 : 0 : }
2186 : :
2187 : : static void
2188 : 987 : nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
2189 : : {
2190 : 987 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2191 : :
2192 [ + - - + : 987 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2193 : : /* no need to print an error, the controller simply does not support ZNS */
2194 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2195 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2196 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
2197 : 0 : return;
2198 : : }
2199 : :
2200 : : /* A zero zasl value means use mdts */
2201 [ - + # # : 987 : if (ctrlr->cdata_zns->zasl) {
# # # # #
# ]
2202 [ # # # # : 0 : uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
# # # # #
# # # # #
# # ]
2203 [ # # # # : 0 : ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
# # # # #
# # # #
# ]
2204 : 0 : } else {
2205 [ # # # # : 987 : ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
# # # # ]
2206 : : }
2207 : :
2208 : 987 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
2209 [ # # # # : 987 : ctrlr->opts.admin_timeout_ms);
# # ]
2210 : 0 : }
2211 : :
2212 : : /**
2213 : : * This function will try to fetch the I/O Command Specific Controller data structure for
2214 : : * each I/O Command Set supported by SPDK.
2215 : : *
2216 : : * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
2217 : : * will be returned. Since we are fetching in a exploratively way, getting an error back
2218 : : * from the controller should not be treated as fatal.
2219 : : *
2220 : : * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
2221 : : *
2222 : : * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
2223 : : * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
2224 : : */
2225 : : static int
2226 : 3302 : nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2227 : : {
2228 : : int rc;
2229 : :
2230 [ + + ]: 3302 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2231 : 3132 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2232 [ + - + - : 2315 : ctrlr->opts.admin_timeout_ms);
+ - ]
2233 : 2315 : return 0;
2234 : : }
2235 : :
2236 : : /*
2237 : : * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
2238 : : * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
2239 : : * which would require additional functions and complexity for no good reason.
2240 : : */
2241 [ - + # # : 987 : assert(!ctrlr->cdata_zns);
# # # # ]
2242 [ # # # # ]: 987 : ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_NUMA_ID_ANY,
2243 : : SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2244 [ - + # # : 987 : if (!ctrlr->cdata_zns) {
# # ]
2245 : 0 : rc = -ENOMEM;
2246 : 0 : goto error;
2247 : : }
2248 : :
2249 : 987 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
2250 [ # # # # : 987 : ctrlr->opts.admin_timeout_ms);
# # ]
2251 : :
2252 : 987 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
2253 [ # # # # ]: 987 : ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
2254 : 0 : nvme_ctrlr_identify_zns_specific_done, ctrlr);
2255 [ - + ]: 987 : if (rc != 0) {
2256 : 0 : goto error;
2257 : : }
2258 : :
2259 : 987 : return 0;
2260 : :
2261 : 0 : error:
2262 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2263 : 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2264 : 0 : return rc;
2265 : 817 : }
2266 : :
2267 : : enum nvme_active_ns_state {
2268 : : NVME_ACTIVE_NS_STATE_IDLE,
2269 : : NVME_ACTIVE_NS_STATE_PROCESSING,
2270 : : NVME_ACTIVE_NS_STATE_DONE,
2271 : : NVME_ACTIVE_NS_STATE_ERROR
2272 : : };
2273 : :
2274 : : typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
2275 : :
2276 : : struct nvme_active_ns_ctx {
2277 : : struct spdk_nvme_ctrlr *ctrlr;
2278 : : uint32_t page_count;
2279 : : uint32_t next_nsid;
2280 : : uint32_t *new_ns_list;
2281 : : nvme_active_ns_ctx_deleter deleter;
2282 : :
2283 : : enum nvme_active_ns_state state;
2284 : : };
2285 : :
2286 : : static struct nvme_active_ns_ctx *
2287 : 3556 : nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
2288 : : {
2289 : : struct nvme_active_ns_ctx *ctx;
2290 : 3556 : uint32_t *new_ns_list = NULL;
2291 : :
2292 : 3556 : ctx = calloc(1, sizeof(*ctx));
2293 [ + + ]: 3556 : if (!ctx) {
2294 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n");
# # # # #
# # # # #
# # # # #
# ]
2295 : 0 : return NULL;
2296 : : }
2297 : :
2298 [ + - + - ]: 3556 : new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
2299 : : NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE);
2300 [ + + ]: 3556 : if (!new_ns_list) {
2301 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n");
# # # # #
# # # # #
# # # # #
# ]
2302 : 0 : free(ctx);
2303 : 0 : return NULL;
2304 : : }
2305 : :
2306 [ + - + - ]: 3556 : ctx->page_count = 1;
2307 [ + - + - ]: 3556 : ctx->new_ns_list = new_ns_list;
2308 [ + - + - ]: 3556 : ctx->ctrlr = ctrlr;
2309 [ + - + - ]: 3556 : ctx->deleter = deleter;
2310 : :
2311 : 3556 : return ctx;
2312 : 817 : }
2313 : :
2314 : : static void
2315 : 3556 : nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
2316 : : {
2317 [ + - + - ]: 3556 : spdk_free(ctx->new_ns_list);
2318 : 3556 : free(ctx);
2319 : 3556 : }
2320 : :
2321 : : static int
2322 : 58108 : nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2323 : : {
2324 : 55668 : struct spdk_nvme_ns tmp, *ns;
2325 : :
2326 [ + + # # ]: 58108 : assert(ctrlr != NULL);
2327 : :
2328 [ + - ]: 58108 : tmp.id = nsid;
2329 [ + - ]: 58108 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
2330 [ + + ]: 58108 : if (ns == NULL) {
2331 : 0 : return -EINVAL;
2332 : : }
2333 : :
2334 : 58108 : nvme_ns_destruct(ns);
2335 [ + - + - ]: 58108 : ns->active = false;
2336 : :
2337 : 58108 : return 0;
2338 : 817 : }
2339 : :
2340 : : static int
2341 : 40113 : nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2342 : : {
2343 : : struct spdk_nvme_ns *ns;
2344 : :
2345 [ + - + + : 40113 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
+ - + - -
+ ]
2346 : 0 : return -EINVAL;
2347 : : }
2348 : :
2349 : : /* Namespaces are constructed on demand, so simply request it. */
2350 : 40113 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2351 [ + + ]: 40113 : if (ns == NULL) {
2352 : 0 : return -ENOMEM;
2353 : : }
2354 : :
2355 [ + - + - ]: 40113 : ns->active = true;
2356 : :
2357 : 40113 : return 0;
2358 : 817 : }
2359 : :
2360 : : static void
2361 : 3553 : nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list,
2362 : : size_t max_entries)
2363 : : {
2364 : 3553 : uint32_t active_ns_count = 0;
2365 : : size_t i;
2366 : : uint32_t nsid;
2367 : : struct spdk_nvme_ns *ns, *tmp_ns;
2368 : : int rc;
2369 : :
2370 : : /* First, remove namespaces that no longer exist */
2371 [ + + + - : 50040 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
- + ]
2372 [ # # # # ]: 46487 : nsid = new_ns_list[0];
2373 : 46487 : active_ns_count = 0;
2374 [ + + ]: 10643061 : while (nsid != 0) {
2375 [ + + # # : 10610819 : if (nsid == ns->id) {
# # ]
2376 : 14245 : break;
2377 : : }
2378 : :
2379 [ # # # # ]: 10596574 : nsid = new_ns_list[active_ns_count++];
2380 : : }
2381 : :
2382 [ + + # # : 46487 : if (nsid != ns->id) {
# # ]
2383 : : /* Did not find this namespace id in the new list. */
2384 [ - + - + : 32242 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id);
- - # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
2385 [ # # # # ]: 32242 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
2386 : 0 : }
2387 : 0 : }
2388 : :
2389 : : /* Next, add new namespaces */
2390 : 3553 : active_ns_count = 0;
2391 [ + + ]: 43666 : for (i = 0; i < max_entries; i++) {
2392 [ + - + - ]: 43666 : nsid = new_ns_list[active_ns_count];
2393 : :
2394 [ + + ]: 43666 : if (nsid == 0) {
2395 : 3553 : break;
2396 : : }
2397 : :
2398 : : /* If the namespace already exists, this will not construct it a second time. */
2399 : 40113 : rc = nvme_ctrlr_construct_namespace(ctrlr, nsid);
2400 [ - + ]: 40113 : if (rc != 0) {
2401 : : /* We can't easily handle a failure here. But just move on. */
2402 [ # # ]: 0 : assert(false);
2403 : : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n");
2404 : : continue;
2405 : : }
2406 : :
2407 : 40113 : active_ns_count++;
2408 : 817 : }
2409 : :
2410 [ + - + - ]: 3553 : ctrlr->active_ns_count = active_ns_count;
2411 : 3553 : }
2412 : :
2413 : : static void
2414 : 3506 : nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2415 : : {
2416 : 3506 : struct nvme_active_ns_ctx *ctx = arg;
2417 : 3506 : uint32_t *new_ns_list = NULL;
2418 : :
2419 [ + + + + : 3506 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2420 [ # # # # ]: 3 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2421 : 3 : goto out;
2422 : : }
2423 : :
2424 [ + - + - : 3503 : ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1];
+ - + - +
- + - + -
+ - ]
2425 [ + + + - : 3503 : if (ctx->next_nsid == 0) {
- + ]
2426 [ + - + - ]: 3488 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2427 : 3488 : goto out;
2428 : : }
2429 : :
2430 [ # # ]: 15 : ctx->page_count++;
2431 [ # # # # ]: 15 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2432 [ # # # # ]: 15 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2433 [ # # # # : 15 : ctx->ctrlr->page_size);
# # # # ]
2434 [ - + ]: 15 : if (!new_ns_list) {
2435 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2436 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2437 : 0 : goto out;
2438 : : }
2439 : :
2440 [ # # # # ]: 15 : ctx->new_ns_list = new_ns_list;
2441 : 15 : nvme_ctrlr_identify_active_ns_async(ctx);
2442 : 15 : return;
2443 : :
2444 : 2674 : out:
2445 [ + + + - : 3491 : if (ctx->deleter) {
- + ]
2446 [ + - + - : 3267 : ctx->deleter(ctx);
- + + - ]
2447 : 817 : }
2448 : 817 : }
2449 : :
2450 : : static void
2451 : 3571 : nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
2452 : : {
2453 [ + - + - ]: 3571 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2454 : : uint32_t i;
2455 : : int rc;
2456 : :
2457 [ + + + - : 3571 : if (ctrlr->cdata.nn == 0) {
+ - + - ]
2458 [ # # # # ]: 48 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2459 : 48 : goto out;
2460 : : }
2461 : :
2462 [ + + + - : 3523 : assert(ctx->new_ns_list != NULL);
+ - # # ]
2463 : :
2464 : : /*
2465 : : * If controller doesn't support active ns list CNS 0x02 dummy up
2466 : : * an active ns list, i.e. all namespaces report as active
2467 : : */
2468 [ + + + + : 3523 : if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
+ - + - +
- + - + -
+ - - + ]
2469 : : uint32_t *new_ns_list;
2470 : :
2471 : : /*
2472 : : * Active NS list must always end with zero element.
2473 : : * So, we allocate for cdata.nn+1.
2474 : : */
2475 [ # # # # : 17 : ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1,
# # # # #
# ]
2476 : : sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0]));
2477 [ # # # # ]: 17 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2478 [ # # # # ]: 17 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2479 [ # # # # : 17 : ctx->ctrlr->page_size);
# # # # ]
2480 [ - + ]: 17 : if (!new_ns_list) {
2481 : 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2482 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2483 : 0 : goto out;
2484 : : }
2485 : :
2486 [ # # # # ]: 17 : ctx->new_ns_list = new_ns_list;
2487 [ # # # # : 17 : ctx->new_ns_list[ctrlr->cdata.nn] = 0;
# # # # #
# # # #
# ]
2488 [ + + # # : 12283 : for (i = 0; i < ctrlr->cdata.nn; i++) {
# # # # ]
2489 [ # # # # : 12266 : ctx->new_ns_list[i] = i + 1;
# # # # ]
2490 : 0 : }
2491 : :
2492 [ # # # # ]: 17 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2493 : 17 : goto out;
2494 : : }
2495 : :
2496 [ + - + - ]: 3506 : ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
2497 [ + - + - ]: 4323 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
2498 [ + - + - : 3506 : &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list),
+ - + - +
- ]
2499 : 817 : nvme_ctrlr_identify_active_ns_async_done, ctx);
2500 [ - + ]: 3506 : if (rc != 0) {
2501 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2502 : 0 : goto out;
2503 : : }
2504 : :
2505 : 3506 : return;
2506 : :
2507 : 65 : out:
2508 [ + + # # : 65 : if (ctx->deleter) {
# # ]
2509 [ # # # # : 50 : ctx->deleter(ctx);
# # # # ]
2510 : 0 : }
2511 : 817 : }
2512 : :
2513 : : static void
2514 : 3317 : _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
2515 : : {
2516 [ + - + - ]: 3317 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2517 : : struct spdk_nvme_ns *ns;
2518 : :
2519 [ + + + - : 3317 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
- + ]
2520 : 0 : nvme_active_ns_ctx_destroy(ctx);
2521 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2522 : 0 : return;
2523 : : }
2524 : :
2525 [ + + + - : 3317 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
+ - # # ]
2526 : :
2527 [ + + - + ]: 3472 : RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) {
2528 : 155 : nvme_ns_free_iocs_specific_data(ns);
2529 : 0 : }
2530 : :
2531 [ + - + - : 3317 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
+ - + - ]
2532 : 3317 : nvme_active_ns_ctx_destroy(ctx);
2533 [ + - + - : 3317 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
+ - ]
2534 : 817 : }
2535 : :
2536 : : static void
2537 : 3317 : _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2538 : : {
2539 : : struct nvme_active_ns_ctx *ctx;
2540 : :
2541 : 3317 : ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
2542 [ + + ]: 3317 : if (!ctx) {
2543 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2544 : 0 : return;
2545 : : }
2546 : :
2547 : 4134 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
2548 [ - + - + : 3317 : ctrlr->opts.admin_timeout_ms);
- + ]
2549 : 3317 : nvme_ctrlr_identify_active_ns_async(ctx);
2550 : 817 : }
2551 : :
2552 : : int
2553 : 239 : nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2554 : : {
2555 : : struct nvme_active_ns_ctx *ctx;
2556 : : int rc;
2557 : :
2558 : 239 : ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
2559 [ - + ]: 239 : if (!ctx) {
2560 : 0 : return -ENOMEM;
2561 : : }
2562 : :
2563 : 239 : nvme_ctrlr_identify_active_ns_async(ctx);
2564 [ + + # # : 269191 : while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
# # ]
2565 [ # # # # ]: 268952 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
2566 [ - + ]: 268952 : if (rc < 0) {
2567 [ # # # # ]: 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2568 : 0 : break;
2569 : : }
2570 : : }
2571 : :
2572 [ + + # # : 239 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
# # ]
2573 : 3 : nvme_active_ns_ctx_destroy(ctx);
2574 : 3 : return -ENXIO;
2575 : : }
2576 : :
2577 [ - + # # : 236 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
# # # # ]
2578 [ # # # # : 236 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
# # # # ]
2579 : 236 : nvme_active_ns_ctx_destroy(ctx);
2580 : :
2581 : 236 : return 0;
2582 : 0 : }
2583 : :
2584 : : static void
2585 : 3006 : nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2586 : : {
2587 : 3006 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2588 [ + - + - ]: 3006 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2589 : : uint32_t nsid;
2590 : : int rc;
2591 : :
2592 [ + - + + : 3006 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2593 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2594 : 0 : return;
2595 : : }
2596 : :
2597 : 3006 : nvme_ns_set_identify_data(ns);
2598 : :
2599 : : /* move on to the next active NS */
2600 [ + - + - ]: 3006 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2601 : 3006 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2602 [ + + ]: 3006 : if (ns == NULL) {
2603 : 3602 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2604 [ - + - + : 2785 : ctrlr->opts.admin_timeout_ms);
- + ]
2605 : 2785 : return;
2606 : : }
2607 [ # # # # ]: 221 : ns->ctrlr = ctrlr;
2608 [ # # # # ]: 221 : ns->id = nsid;
2609 : :
2610 : 221 : rc = nvme_ctrlr_identify_ns_async(ns);
2611 [ - + ]: 221 : if (rc) {
2612 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2613 : 0 : }
2614 : 817 : }
2615 : :
2616 : : static int
2617 : 3006 : nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
2618 : : {
2619 [ + - + - ]: 3006 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2620 : : struct spdk_nvme_ns_data *nsdata;
2621 : :
2622 [ + - ]: 3006 : nsdata = &ns->nsdata;
2623 : :
2624 : 3823 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
2625 [ + - + - : 3006 : ctrlr->opts.admin_timeout_ms);
+ - ]
2626 [ + - + - : 3006 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
+ - + - ]
2627 : 817 : nsdata, sizeof(*nsdata),
2628 : 817 : nvme_ctrlr_identify_ns_async_done, ns);
2629 : : }
2630 : :
2631 : : static int
2632 : 3287 : nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2633 : : {
2634 : : uint32_t nsid;
2635 : : struct spdk_nvme_ns *ns;
2636 : : int rc;
2637 : :
2638 : 3287 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2639 : 3287 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2640 [ + + ]: 3287 : if (ns == NULL) {
2641 : : /* No active NS, move on to the next state */
2642 : 502 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2643 [ # # # # : 502 : ctrlr->opts.admin_timeout_ms);
# # ]
2644 : 502 : return 0;
2645 : : }
2646 : :
2647 [ + - + - ]: 2785 : ns->ctrlr = ctrlr;
2648 [ + - + - ]: 2785 : ns->id = nsid;
2649 : :
2650 : 2785 : rc = nvme_ctrlr_identify_ns_async(ns);
2651 [ + + ]: 2785 : if (rc) {
2652 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2653 : 0 : }
2654 : :
2655 : 2785 : return rc;
2656 : 817 : }
2657 : :
2658 : : static int
2659 : 1797 : nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2660 : : {
2661 : : uint32_t nsid;
2662 : : struct spdk_nvme_ns *ns;
2663 : : int rc;
2664 : :
2665 [ + + ]: 1797 : if (!prev_nsid) {
2666 : 993 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2667 : 0 : } else {
2668 : : /* move on to the next active NS */
2669 : 804 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2670 : : }
2671 : :
2672 : 1797 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2673 [ + + ]: 1797 : if (ns == NULL) {
2674 : : /* No first/next active NS, move on to the next state */
2675 : 665 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2676 [ # # # # : 665 : ctrlr->opts.admin_timeout_ms);
# # ]
2677 : 665 : return 0;
2678 : : }
2679 : :
2680 : : /* loop until we find a ns which has (supported) iocs specific data */
2681 [ + + ]: 1153 : while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2682 [ # # # # ]: 349 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2683 : 349 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2684 [ + + ]: 349 : if (ns == NULL) {
2685 : : /* no namespace with (supported) iocs specific data found */
2686 : 328 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2687 [ # # # # : 328 : ctrlr->opts.admin_timeout_ms);
# # ]
2688 : 328 : return 0;
2689 : : }
2690 : : }
2691 : :
2692 : 804 : rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2693 [ + + ]: 804 : if (rc) {
2694 : 3 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2695 : 0 : }
2696 : :
2697 : 804 : return rc;
2698 : 0 : }
2699 : :
2700 : : static void
2701 : 2 : nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2702 : : {
2703 : 2 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2704 [ # # # # ]: 2 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2705 : :
2706 [ + - - + : 2 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2707 : 0 : nvme_ns_free_zns_specific_data(ns);
2708 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2709 : 0 : return;
2710 : : }
2711 : :
2712 [ # # # # ]: 2 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2713 : 0 : }
2714 : :
2715 : : static int
2716 : 8 : nvme_ctrlr_identify_ns_zns_specific_async(struct spdk_nvme_ns *ns)
2717 : : {
2718 [ # # # # ]: 8 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2719 : : int rc;
2720 : :
2721 [ - + # # : 8 : assert(!ns->nsdata_zns);
# # # # ]
2722 [ # # # # ]: 8 : ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_NUMA_ID_ANY,
2723 : : SPDK_MALLOC_SHARE);
2724 [ - + # # : 8 : if (!ns->nsdata_zns) {
# # ]
2725 : 0 : return -ENOMEM;
2726 : : }
2727 : :
2728 : 8 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2729 [ # # # # : 8 : ctrlr->opts.admin_timeout_ms);
# # ]
2730 [ # # # # : 8 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
# # # # #
# # # ]
2731 [ # # # # ]: 8 : ns->nsdata_zns, sizeof(*ns->nsdata_zns),
2732 : 0 : nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2733 [ + + ]: 8 : if (rc) {
2734 : 3 : nvme_ns_free_zns_specific_data(ns);
2735 : 0 : }
2736 : :
2737 : 8 : return rc;
2738 : 0 : }
2739 : :
2740 : : static void
2741 : 796 : nvme_ctrlr_identify_ns_nvm_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2742 : : {
2743 : 796 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2744 [ # # # # ]: 796 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2745 : :
2746 [ + - - + : 796 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
2747 : 0 : nvme_ns_free_nvm_specific_data(ns);
2748 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2749 : 0 : return;
2750 : : }
2751 : :
2752 [ # # # # ]: 796 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2753 : 0 : }
2754 : :
2755 : : static int
2756 : 796 : nvme_ctrlr_identify_ns_nvm_specific_async(struct spdk_nvme_ns *ns)
2757 : : {
2758 [ # # # # ]: 796 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2759 : : int rc;
2760 : :
2761 [ - + # # : 796 : assert(!ns->nsdata_nvm);
# # # # ]
2762 [ # # # # ]: 796 : ns->nsdata_nvm = spdk_zmalloc(sizeof(*ns->nsdata_nvm), 64, NULL, SPDK_ENV_NUMA_ID_ANY,
2763 : : SPDK_MALLOC_SHARE);
2764 [ - + # # : 796 : if (!ns->nsdata_nvm) {
# # ]
2765 : 0 : return -ENOMEM;
2766 : : }
2767 : :
2768 : 796 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2769 [ # # # # : 796 : ctrlr->opts.admin_timeout_ms);
# # ]
2770 [ # # # # : 796 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
# # # # #
# # # ]
2771 [ # # # # ]: 796 : ns->nsdata_nvm, sizeof(*ns->nsdata_nvm),
2772 : 0 : nvme_ctrlr_identify_ns_nvm_specific_async_done, ns);
2773 [ - + ]: 796 : if (rc) {
2774 : 0 : nvme_ns_free_nvm_specific_data(ns);
2775 : 0 : }
2776 : :
2777 : 796 : return rc;
2778 : 0 : }
2779 : :
2780 : : static int
2781 : 804 : nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2782 : : {
2783 [ + + - # : 804 : switch (ns->csi) {
# # # ]
2784 : 8 : case SPDK_NVME_CSI_ZNS:
2785 : 8 : return nvme_ctrlr_identify_ns_zns_specific_async(ns);
2786 : 796 : case SPDK_NVME_CSI_NVM:
2787 [ + - # # : 796 : if (ns->ctrlr->cdata.ctratt.bits.elbas) {
# # # # #
# # # #
# ]
2788 : 796 : return nvme_ctrlr_identify_ns_nvm_specific_async(ns);
2789 : : }
2790 : : /* fallthrough */
2791 : : default:
2792 : : /*
2793 : : * This switch must handle all cases for which
2794 : : * nvme_ns_has_supported_iocs_specific_data() returns true,
2795 : : * other cases should never happen.
2796 : : */
2797 [ # # ]: 0 : assert(0);
2798 : : }
2799 : :
2800 : : return -EINVAL;
2801 : 0 : }
2802 : :
2803 : : static int
2804 : 3287 : nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2805 : : {
2806 [ + + ]: 3287 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2807 : : /* Multi IOCS not supported/enabled, move on to the next state */
2808 : 3117 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2809 [ + - + - : 2300 : ctrlr->opts.admin_timeout_ms);
+ - ]
2810 : 2300 : return 0;
2811 : : }
2812 : :
2813 : 987 : return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2814 : 817 : }
2815 : :
2816 : : static void
2817 : 2844 : nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2818 : : {
2819 : 2844 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2820 [ + - + - ]: 2844 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2821 : : uint32_t nsid;
2822 : : int rc;
2823 : :
2824 [ + + + + : 2844 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2825 : : /*
2826 : : * Many controllers claim to be compatible with NVMe 1.3, however,
2827 : : * they do not implement NS ID Desc List. Therefore, instead of setting
2828 : : * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion
2829 : : * error and move on to the next state.
2830 : : *
2831 : : * The proper way is to create a new quirk for controllers that violate
2832 : : * the NVMe 1.3 spec by not supporting NS ID Desc List.
2833 : : * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since
2834 : : * it is too generic and was added in order to handle controllers that
2835 : : * violate the NVMe 1.1 spec by not supporting ACTIVE LIST).
2836 : : */
2837 : 15 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2838 [ # # # # : 15 : ctrlr->opts.admin_timeout_ms);
# # ]
2839 : 15 : return;
2840 : : }
2841 : :
2842 : 2829 : nvme_ns_set_id_desc_list_data(ns);
2843 : :
2844 : : /* move on to the next active NS */
2845 [ + - + - ]: 2829 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2846 : 2829 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2847 [ + + ]: 2829 : if (ns == NULL) {
2848 : 3456 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2849 [ - + - + : 2641 : ctrlr->opts.admin_timeout_ms);
- + ]
2850 : 2641 : return;
2851 : : }
2852 : :
2853 : 188 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2854 [ - + ]: 188 : if (rc) {
2855 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2856 : 0 : }
2857 : 815 : }
2858 : :
2859 : : static int
2860 : 2844 : nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2861 : : {
2862 [ + - + - ]: 2844 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2863 : :
2864 [ + + + - ]: 2844 : memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2865 : :
2866 : 3659 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2867 [ + - + - : 2844 : ctrlr->opts.admin_timeout_ms);
+ - ]
2868 [ + - + - ]: 3863 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2869 [ + - + - : 2844 : 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
+ - ]
2870 : 815 : nvme_ctrlr_identify_id_desc_async_done, ns);
2871 : : }
2872 : :
2873 : : static int
2874 : 3287 : nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2875 : : {
2876 : : uint32_t nsid;
2877 : : struct spdk_nvme_ns *ns;
2878 : : int rc;
2879 : :
2880 [ + + + - : 4104 : if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
+ - + - +
- + + +
+ ]
2881 [ + + + - : 155 : !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
+ - + - ]
2882 [ + + + - ]: 3134 : (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2883 [ + + + + : 155 : NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
2884 : : /* NS ID Desc List not supported, move on to the next state */
2885 : 157 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2886 [ + - + - : 155 : ctrlr->opts.admin_timeout_ms);
+ - ]
2887 : 155 : return 0;
2888 : : }
2889 : :
2890 : 3132 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2891 : 3132 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2892 [ + + ]: 3132 : if (ns == NULL) {
2893 : : /* No active NS, move on to the next state */
2894 : 476 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2895 [ # # # # : 476 : ctrlr->opts.admin_timeout_ms);
# # ]
2896 : 476 : return 0;
2897 : : }
2898 : :
2899 : 2656 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2900 [ + + ]: 2656 : if (rc) {
2901 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2902 : 0 : }
2903 : :
2904 : 2656 : return rc;
2905 : 817 : }
2906 : :
2907 : : static void
2908 : 3302 : nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2909 : : {
2910 [ + + ]: 3302 : if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
2911 [ + + + - : 2377 : if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
+ - + - +
- ]
2912 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
2913 : : ctrlr->cdata.nvmf_specific.ioccsz);
2914 [ # # # # : 0 : ctrlr->cdata.nvmf_specific.ioccsz = 4;
# # # # ]
2915 [ # # ]: 0 : assert(0);
2916 : : }
2917 [ + - + - : 2377 : ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
+ - + - +
- + - ]
2918 [ + - + - : 2377 : ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
+ - + - +
- + - ]
2919 : 808 : }
2920 : 3302 : }
2921 : :
2922 : : static void
2923 : 3302 : nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2924 : : {
2925 : : uint32_t cq_allocated, sq_allocated, min_allocated, i;
2926 : 3302 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2927 : :
2928 [ + - + + : 3302 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
2929 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n");
# # # # #
# # # # #
# # # # #
# ]
2930 [ # # # # : 0 : ctrlr->opts.num_io_queues = 0;
# # ]
2931 : 0 : } else {
2932 : : /*
2933 : : * Data in cdw0 is 0-based.
2934 : : * Lower 16-bits indicate number of submission queues allocated.
2935 : : * Upper 16-bits indicate number of completion queues allocated.
2936 : : */
2937 [ + - + - ]: 3302 : sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2938 [ + - + - : 3302 : cq_allocated = (cpl->cdw0 >> 16) + 1;
+ - ]
2939 : :
2940 : : /*
2941 : : * For 1:1 queue mapping, set number of allocated queues to be minimum of
2942 : : * submission and completion queues.
2943 : : */
2944 [ - + ]: 3302 : min_allocated = spdk_min(sq_allocated, cq_allocated);
2945 : :
2946 : : /* Set number of queues to be minimum of requested and actually allocated. */
2947 [ + - + - : 3302 : ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
+ - + - #
# # # # #
+ - + - +
- ]
2948 : : }
2949 : :
2950 [ + - + - : 3302 : ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
+ - + - +
- ]
2951 [ + + + - : 3302 : if (ctrlr->free_io_qids == NULL) {
+ - ]
2952 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2953 : 0 : return;
2954 : : }
2955 : :
2956 : : /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2957 [ + + + - : 373872 : for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
+ - + + ]
2958 : 370570 : spdk_nvme_ctrlr_free_qid(ctrlr, i);
2959 : 103761 : }
2960 : :
2961 : 4119 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
2962 [ + - + - : 3302 : ctrlr->opts.admin_timeout_ms);
+ - ]
2963 : 817 : }
2964 : :
2965 : : static int
2966 : 3302 : nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2967 : : {
2968 : : int rc;
2969 : :
2970 [ + + + - : 3302 : if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
+ - - + ]
2971 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
2972 : : ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2973 [ # # # # : 0 : ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
# # ]
2974 [ + + + - : 3302 : } else if (ctrlr->opts.num_io_queues < 1) {
+ - + - ]
2975 [ - + # # : 39 : NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n");
# # # # #
# # # # #
# # # # #
# ]
2976 [ # # # # : 39 : ctrlr->opts.num_io_queues = 1;
# # ]
2977 : 0 : }
2978 : :
2979 : 4119 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2980 [ + - + - : 3302 : ctrlr->opts.admin_timeout_ms);
+ - ]
2981 : :
2982 [ + - + - : 3302 : rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
+ - ]
2983 : 817 : nvme_ctrlr_set_num_queues_done, ctrlr);
2984 [ - + ]: 3302 : if (rc != 0) {
2985 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2986 : 0 : return rc;
2987 : : }
2988 : :
2989 : 3302 : return 0;
2990 : 817 : }
2991 : :
2992 : : static void
2993 : 2602 : nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2994 : : {
2995 : : uint32_t keep_alive_interval_us;
2996 : 2602 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2997 : :
2998 [ + + + + : 2602 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ - ]
2999 [ + - # # : 6 : if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
# # # # #
# ]
3000 [ + + # # : 6 : (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
# # ]
3001 [ - + - + : 3 : NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
3002 : 0 : } else {
3003 [ - + # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3004 : : cpl->status.sc, cpl->status.sct);
3005 [ # # # # : 3 : ctrlr->opts.keep_alive_timeout_ms = 0;
# # ]
3006 : 3 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3007 : 3 : return;
3008 : : }
3009 : 0 : } else {
3010 [ + + + - : 2596 : if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
+ - + - +
- + + ]
3011 [ + + + + : 79 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n",
+ + # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3012 : : cpl->cdw0);
3013 : 7 : }
3014 : :
3015 [ + - + - : 2596 : ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
+ - + - +
- ]
3016 : : }
3017 : :
3018 [ + + + - : 2599 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
+ - + + ]
3019 [ + - + - ]: 76 : ctrlr->keep_alive_interval_ticks = 0;
3020 : 7 : } else {
3021 [ + - + - : 2523 : keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
+ - + - ]
3022 : :
3023 [ + + + + : 2523 : NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us);
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
3024 : :
3025 [ + - + - : 2523 : ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
+ - ]
3026 : : UINT64_C(1000000);
3027 : :
3028 : : /* Schedule the first Keep Alive to be sent as soon as possible. */
3029 [ + - + - ]: 2523 : ctrlr->next_keep_alive_tick = spdk_get_ticks();
3030 : : }
3031 : :
3032 [ + + ]: 2599 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3033 : 152 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
3034 : 0 : } else {
3035 : 3262 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
3036 [ + - + - : 2447 : ctrlr->opts.admin_timeout_ms);
+ - ]
3037 : : }
3038 : 815 : }
3039 : :
3040 : : static int
3041 : 3463 : nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
3042 : : {
3043 : : int rc;
3044 : :
3045 [ + + + - : 3463 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
+ - + - ]
3046 [ - + ]: 143 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3047 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
3048 : 0 : } else {
3049 : 143 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
3050 [ # # # # : 143 : ctrlr->opts.admin_timeout_ms);
# # ]
3051 : : }
3052 : 143 : return 0;
3053 : : }
3054 : :
3055 : : /* Note: Discovery controller identify data does not populate KAS according to spec. */
3056 [ + + + + : 3320 : if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) {
+ - + - +
+ ]
3057 [ + + + + : 718 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n");
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
3058 [ + - + - : 718 : ctrlr->opts.keep_alive_timeout_ms = 0;
+ - ]
3059 : 720 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
3060 [ + - + - : 718 : ctrlr->opts.admin_timeout_ms);
+ - ]
3061 : 718 : return 0;
3062 : : }
3063 : :
3064 : 3417 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
3065 [ + - + - : 2602 : ctrlr->opts.admin_timeout_ms);
+ - ]
3066 : :
3067 : : /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
3068 : 3417 : rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
3069 : 815 : nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
3070 [ + + ]: 2602 : if (rc != 0) {
3071 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc);
# # # # #
# # # # #
# # # # #
# ]
3072 [ # # # # : 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
# # ]
3073 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3074 : 0 : return rc;
3075 : : }
3076 : :
3077 : 2602 : return 0;
3078 : 817 : }
3079 : :
3080 : : static void
3081 : 0 : nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
3082 : : {
3083 : 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3084 : :
3085 [ # # # # : 0 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
3086 : : /*
3087 : : * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
3088 : : * is optional.
3089 : : */
3090 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3091 : : cpl->status.sc, cpl->status.sct);
3092 : 0 : } else {
3093 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3094 : : }
3095 : :
3096 [ # # # # : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
# # ]
3097 : 0 : }
3098 : :
3099 : : static int
3100 : 3287 : nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
3101 : : {
3102 : : uint8_t *host_id;
3103 : : uint32_t host_id_size;
3104 : : int rc;
3105 : :
3106 [ + + + - : 3287 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
+ - + + ]
3107 : : /*
3108 : : * NVMe-oF sends the host ID during Connect and doesn't allow
3109 : : * Set Features - Host Identifier after Connect, so we don't need to do anything here.
3110 : : */
3111 [ + + + + : 2483 : NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n");
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
3112 [ + - + - : 2483 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
+ - ]
3113 : 2483 : return 0;
3114 : : }
3115 : :
3116 [ + + + - : 804 : if (ctrlr->cdata.ctratt.bits.host_id_exhid_supported) {
+ - + - -
+ ]
3117 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3118 [ # # # # ]: 0 : host_id = ctrlr->opts.extended_host_id;
3119 : 0 : host_id_size = sizeof(ctrlr->opts.extended_host_id);
3120 : 0 : } else {
3121 [ + + + + : 804 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n");
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
3122 [ + - + - ]: 804 : host_id = ctrlr->opts.host_id;
3123 : 804 : host_id_size = sizeof(ctrlr->opts.host_id);
3124 : : }
3125 : :
3126 : : /* If the user specified an all-zeroes host identifier, don't send the command. */
3127 [ + - ]: 804 : if (spdk_mem_all_zero(host_id, host_id_size)) {
3128 [ + + + + : 804 : NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n");
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
3129 [ + - + - : 804 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
+ - ]
3130 : 804 : return 0;
3131 : : }
3132 : :
3133 [ # # # # : 0 : SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
# # ]
3134 : :
3135 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
3136 [ # # # # : 0 : ctrlr->opts.admin_timeout_ms);
# # ]
3137 : :
3138 : 0 : rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
3139 [ # # ]: 0 : if (rc != 0) {
3140 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc);
# # # # #
# # # # #
# # # # #
# ]
3141 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3142 : 0 : return rc;
3143 : : }
3144 : :
3145 : 0 : return 0;
3146 : 817 : }
3147 : :
3148 : : void
3149 : 188 : nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
3150 : : {
3151 : : uint32_t nsid;
3152 : : struct spdk_nvme_ns *ns;
3153 : :
3154 [ # # ]: 188 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
3155 [ + + ]: 470 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) {
3156 : 282 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
3157 : 282 : nvme_ns_construct(ns, nsid, ctrlr);
3158 : 0 : }
3159 : 188 : }
3160 : :
3161 : : static int
3162 : 188 : nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr)
3163 : : {
3164 : : struct nvme_completion_poll_status *status;
3165 : 188 : int rc = -ENOMEM;
3166 : 188 : char *buffer = NULL;
3167 : : uint32_t nsid;
3168 : 188 : size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t));
3169 : :
3170 [ - + # # : 188 : if (ctrlr->opts.disable_read_changed_ns_list_log_page) {
# # # # ]
3171 : 0 : return 0;
3172 : : }
3173 : :
3174 : 188 : buffer = spdk_dma_zmalloc(buf_size, 4096, NULL);
3175 [ - + ]: 188 : if (!buffer) {
3176 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting "
# # # # #
# # # # #
# # # # #
# ]
3177 : : "changed ns log.\n");
3178 : 0 : return rc;
3179 : : }
3180 : :
3181 : 188 : status = calloc(1, sizeof(*status));
3182 [ - + ]: 188 : if (!status) {
3183 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
3184 : 0 : goto free_buffer;
3185 : : }
3186 : :
3187 : 188 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr,
3188 : : SPDK_NVME_LOG_CHANGED_NS_LIST,
3189 : : SPDK_NVME_GLOBAL_NS_TAG,
3190 : 0 : buffer, buf_size, 0,
3191 : 0 : nvme_completion_poll_cb, status);
3192 : :
3193 [ - + ]: 188 : if (rc) {
3194 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc);
# # # # #
# # # # #
# # # # #
# ]
3195 : 0 : free(status);
3196 : 0 : goto free_buffer;
3197 : : }
3198 : :
3199 [ # # # # ]: 188 : rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status,
3200 [ # # # # : 188 : ctrlr->opts.admin_timeout_ms * 1000);
# # ]
3201 [ + + + - : 188 : if (!status->timed_out) {
# # # # ]
3202 : 188 : free(status);
3203 : 0 : }
3204 : :
3205 [ - + ]: 188 : if (rc) {
3206 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc);
# # # # #
# # # # #
# # # # #
# ]
3207 : 0 : goto free_buffer;
3208 : : }
3209 : :
3210 : : /* only check the case of overflow. */
3211 : 188 : nsid = from_le32(buffer);
3212 [ + - ]: 188 : if (nsid == 0xffffffffu) {
3213 [ # # # # : 0 : NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n");
# # # # #
# # # # #
# # # # #
# ]
3214 : 0 : }
3215 : :
3216 : 188 : free_buffer:
3217 : 188 : spdk_dma_free(buffer);
3218 : 188 : return rc;
3219 : 0 : }
3220 : :
3221 : : static void
3222 : 393 : nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr,
3223 : : const struct spdk_nvme_cpl *cpl)
3224 : : {
3225 : : union spdk_nvme_async_event_completion event;
3226 : : struct spdk_nvme_ctrlr_process *active_proc;
3227 : : int rc;
3228 : :
3229 [ + - + - ]: 393 : event.raw = cpl->cdw0;
3230 : :
3231 [ + + # # ]: 393 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3232 [ + + ]: 307 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
3233 : 188 : nvme_ctrlr_clear_changed_ns_log(ctrlr);
3234 : :
3235 : 188 : rc = nvme_ctrlr_identify_active_ns(ctrlr);
3236 [ - + ]: 188 : if (rc) {
3237 : 0 : return;
3238 : : }
3239 : 188 : nvme_ctrlr_update_namespaces(ctrlr);
3240 : 188 : nvme_io_msg_ctrlr_update(ctrlr);
3241 : 0 : }
3242 : :
3243 [ + + # # ]: 393 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3244 [ + + ]: 307 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
3245 [ + + + + : 103 : if (!ctrlr->opts.disable_read_ana_log_page) {
# # # # #
# ]
3246 : 3 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
3247 [ - + ]: 3 : if (rc) {
3248 : 0 : return;
3249 : : }
3250 : 3 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
3251 : 0 : ctrlr);
3252 : 0 : }
3253 : 0 : }
3254 : :
3255 : 393 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3256 [ + - + + : 393 : if (active_proc && active_proc->aer_cb_fn) {
+ - - + ]
3257 [ # # # # : 207 : active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
# # # # #
# # # ]
3258 : 0 : }
3259 : 11 : }
3260 : :
3261 : : static void
3262 : 988 : nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr,
3263 : : const struct spdk_nvme_cpl *cpl)
3264 : : {
3265 : : struct spdk_nvme_ctrlr_aer_completion *nvme_event;
3266 : : struct spdk_nvme_ctrlr_process *proc;
3267 : :
3268 : : /* Add async event to each process objects event list */
3269 [ + + + - : 2011 : TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
+ - + + +
- + - +
- ]
3270 : : /* Must be shared memory so other processes can access */
3271 : 1023 : nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_NUMA_ID_ANY, SPDK_MALLOC_SHARE);
3272 [ + + ]: 1023 : if (!nvme_event) {
3273 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n");
# # # # #
# # # # #
# # # # #
# ]
3274 : 0 : return;
3275 : : }
3276 [ + - ]: 1023 : nvme_event->cpl = *cpl;
3277 : :
3278 [ + - + - : 1023 : STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link);
+ - + - +
- + - + -
+ - + - +
- + - +
- ]
3279 : 11 : }
3280 : 11 : }
3281 : :
3282 : : static void
3283 : 50456418 : nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr)
3284 : : {
3285 : : struct spdk_nvme_ctrlr_aer_completion *nvme_event, *nvme_event_tmp;
3286 : : struct spdk_nvme_ctrlr_process *active_proc;
3287 : :
3288 : 50456418 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3289 : :
3290 [ + + + - : 50456811 : STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) {
+ - + + +
- + - + -
+ + ]
3291 [ + - + + : 393 : STAILQ_REMOVE(&active_proc->async_events, nvme_event,
+ - - + +
- + - + -
+ - + - +
- + - + -
+ - - + +
- + - + -
+ - + - #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
3292 : : spdk_nvme_ctrlr_aer_completion, link);
3293 [ + - ]: 393 : nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl);
3294 : 393 : spdk_free(nvme_event);
3295 : :
3296 : 11 : }
3297 : 50456418 : }
3298 : :
3299 : : static void
3300 : 14172 : nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
3301 : : {
3302 : 14172 : struct nvme_async_event_request *aer = arg;
3303 [ + - + - ]: 14172 : struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
3304 : :
3305 [ + - + - : 17451 : if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
+ - + - +
+ ]
3306 [ + + + - : 14172 : cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
+ - ]
3307 : : /*
3308 : : * This is simulated when controller is being shut down, to
3309 : : * effectively abort outstanding asynchronous event requests
3310 : : * and make sure all memory is freed. Do not repost the
3311 : : * request in this case.
3312 : : */
3313 : 13184 : return;
3314 : : }
3315 : :
3316 [ + + + - : 988 : if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
+ - - + #
# ]
3317 [ # # # # : 0 : cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
# # ]
3318 : : /*
3319 : : * SPDK will only send as many AERs as the device says it supports,
3320 : : * so this status code indicates an out-of-spec device. Do not repost
3321 : : * the request in this case.
3322 : : */
3323 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n"
# # # # #
# # # # #
# # # # #
# ]
3324 : : "handling. Do not repost this AER.\n");
3325 : 0 : return;
3326 : : }
3327 : :
3328 : : /* Add the events to the list */
3329 : 988 : nvme_ctrlr_queue_async_event(ctrlr, cpl);
3330 : :
3331 : : /* If the ctrlr was removed or in the destruct state, we should not send aer again */
3332 [ + + + + : 988 : if (ctrlr->is_removed || ctrlr->is_destructed) {
+ + + + +
- + - + -
+ - ]
3333 : 292 : return;
3334 : : }
3335 : :
3336 : : /*
3337 : : * Repost another asynchronous event request to replace the one
3338 : : * that just completed.
3339 : : */
3340 [ + + ]: 696 : if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
3341 : : /*
3342 : : * We can't do anything to recover from a failure here,
3343 : : * so just print a warning message and leave the AER unsubmitted.
3344 : : */
3345 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n");
# # # # #
# # # # #
# # # # #
# ]
3346 : 0 : }
3347 : 3279 : }
3348 : :
3349 : : static int
3350 : 14329 : nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
3351 : : struct nvme_async_event_request *aer)
3352 : : {
3353 : : struct nvme_request *req;
3354 : :
3355 [ + - + - ]: 14329 : aer->ctrlr = ctrlr;
3356 [ + - + - ]: 14329 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
3357 [ + - + - ]: 14329 : aer->req = req;
3358 [ + + ]: 14329 : if (req == NULL) {
3359 : 0 : return -1;
3360 : : }
3361 : :
3362 [ + - + - ]: 14329 : req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
3363 : 14329 : return nvme_ctrlr_submit_admin_request(ctrlr, req);
3364 : 3279 : }
3365 : :
3366 : : static void
3367 : 3454 : nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
3368 : : {
3369 : : struct nvme_async_event_request *aer;
3370 : : int rc;
3371 : : uint32_t i;
3372 : 3454 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3373 : :
3374 [ + - + + : 3454 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3375 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n");
# # # # #
# # # # #
# # # # #
# ]
3376 [ # # # # ]: 0 : ctrlr->num_aers = 0;
3377 : 0 : } else {
3378 : : /* aerl is a zero-based value, so we need to add 1 here. */
3379 [ + - + - : 3454 : ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
+ - + - -
+ + - + -
+ - + - +
- + - ]
3380 : : }
3381 : :
3382 [ + + + - : 17087 : for (i = 0; i < ctrlr->num_aers; i++) {
+ + ]
3383 [ + - + - : 13633 : aer = &ctrlr->aer[i];
+ - ]
3384 : 13633 : rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
3385 [ + + ]: 13633 : if (rc) {
3386 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
# # # # #
# # # # #
# # # # #
# ]
3387 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3388 : 0 : return;
3389 : : }
3390 : 3268 : }
3391 [ + - + - : 3454 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms);
+ - ]
3392 : 817 : }
3393 : :
3394 : : static int
3395 : 3454 : nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
3396 : : {
3397 : : union spdk_nvme_feat_async_event_configuration config;
3398 : : int rc;
3399 : :
3400 : 3454 : config.raw = 0;
3401 : :
3402 [ + + ]: 3454 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3403 : 152 : config.bits.discovery_log_change_notice = 1;
3404 : 0 : } else {
3405 : 3302 : config.bits.crit_warn.bits.available_spare = 1;
3406 : 3302 : config.bits.crit_warn.bits.temperature = 1;
3407 : 3302 : config.bits.crit_warn.bits.device_reliability = 1;
3408 : 3302 : config.bits.crit_warn.bits.read_only = 1;
3409 : 3302 : config.bits.crit_warn.bits.volatile_memory_backup = 1;
3410 : :
3411 [ + + + - : 3302 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
+ - + - +
- - + ]
3412 [ + + + - : 3252 : if (ctrlr->cdata.oaes.ns_attribute_notices) {
+ - + + ]
3413 : 3125 : config.bits.ns_attr_notice = 1;
3414 : 815 : }
3415 [ + + + - : 3252 : if (ctrlr->cdata.oaes.fw_activation_notices) {
+ - + + ]
3416 : 137 : config.bits.fw_activation_notice = 1;
3417 : 2 : }
3418 [ + + + - : 3252 : if (ctrlr->cdata.oaes.ana_change_notices) {
+ - + - ]
3419 : 339 : config.bits.ana_change_notice = 1;
3420 : 0 : }
3421 : 817 : }
3422 [ + + + + : 3302 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
+ - + - +
- + + + -
+ - + - +
- ]
3423 : 23 : config.bits.telemetry_log_notice = 1;
3424 : 0 : }
3425 : : }
3426 : :
3427 : 4271 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
3428 [ + - + - : 3454 : ctrlr->opts.admin_timeout_ms);
+ - ]
3429 : :
3430 : 4271 : rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
3431 : : nvme_ctrlr_configure_aer_done,
3432 : 817 : ctrlr);
3433 [ - + ]: 3454 : if (rc != 0) {
3434 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3435 : 0 : return rc;
3436 : : }
3437 : :
3438 : 3454 : return 0;
3439 : 817 : }
3440 : :
3441 : : struct spdk_nvme_ctrlr_process *
3442 : 153288642 : nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
3443 : : {
3444 : : struct spdk_nvme_ctrlr_process *active_proc;
3445 : :
3446 [ + + + - : 282358694 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
+ - + + #
# # # #
# ]
3447 [ + + + - : 282354904 : if (active_proc->pid == pid) {
- + ]
3448 : 153284852 : return active_proc;
3449 : : }
3450 : 0 : }
3451 : :
3452 : 3790 : return NULL;
3453 : 526486 : }
3454 : :
3455 : : struct spdk_nvme_ctrlr_process *
3456 : 153284686 : nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
3457 : : {
3458 : 153284686 : return nvme_ctrlr_get_process(ctrlr, getpid());
3459 : : }
3460 : :
3461 : : /**
3462 : : * This function will be called when a process is using the controller.
3463 : : * 1. For the primary process, it is called when constructing the controller.
3464 : : * 2. For the secondary process, it is called at probing the controller.
3465 : : * Note: will check whether the process is already added for the same process.
3466 : : */
3467 : : int
3468 : 3612 : nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
3469 : : {
3470 : : struct spdk_nvme_ctrlr_process *ctrlr_proc;
3471 : 3612 : pid_t pid = getpid();
3472 : :
3473 : : /* Check whether the process is already added or not */
3474 [ + + ]: 3612 : if (nvme_ctrlr_get_process(ctrlr, pid)) {
3475 : 41 : return 0;
3476 : : }
3477 : :
3478 : : /* Initialize the per process properties for this ctrlr */
3479 : 3571 : ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
3480 : : 64, NULL, SPDK_ENV_NUMA_ID_ANY, SPDK_MALLOC_SHARE);
3481 [ + + ]: 3571 : if (ctrlr_proc == NULL) {
3482 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n");
# # # # #
# # # # #
# # # # #
# ]
3483 : :
3484 : 0 : return -1;
3485 : : }
3486 : :
3487 [ + - + - ]: 3571 : ctrlr_proc->is_primary = spdk_process_is_primary();
3488 [ + - + - ]: 3571 : ctrlr_proc->pid = pid;
3489 [ + - + - : 3571 : STAILQ_INIT(&ctrlr_proc->active_reqs);
+ - + - +
- + - + -
+ - ]
3490 [ + - + - ]: 3571 : ctrlr_proc->devhandle = devhandle;
3491 [ + - + - ]: 3571 : ctrlr_proc->ref = 0;
3492 [ + - + - : 3571 : TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
+ - + - +
- + - + -
+ - ]
3493 [ + - + - : 3571 : STAILQ_INIT(&ctrlr_proc->async_events);
+ - + - +
- + - + -
+ - ]
3494 : :
3495 [ + - + - : 3571 : TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - + -
+ - ]
3496 : :
3497 : 3571 : return 0;
3498 : 817 : }
3499 : :
3500 : : /**
3501 : : * This function will be called when the process detaches the controller.
3502 : : * Note: the ctrlr_lock must be held when calling this function.
3503 : : */
3504 : : static void
3505 : 228 : nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
3506 : : struct spdk_nvme_ctrlr_process *proc)
3507 : : {
3508 : : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3509 : :
3510 [ - + # # : 228 : assert(STAILQ_EMPTY(&proc->active_reqs));
# # # # #
# ]
3511 : :
3512 [ + + # # : 248 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
# # # # #
# # # # #
# # ]
3513 : 20 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3514 : 0 : }
3515 : :
3516 [ + + # # : 228 : TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3517 : :
3518 [ + - # # : 228 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
# # # # ]
3519 [ # # # # ]: 228 : spdk_pci_device_detach(proc->devhandle);
3520 : 0 : }
3521 : :
3522 : 228 : spdk_free(proc);
3523 : 228 : }
3524 : :
3525 : : /**
3526 : : * This function will be called when the process exited unexpectedly
3527 : : * in order to free any incomplete nvme request, allocated IO qpairs
3528 : : * and allocated memory.
3529 : : * Note: the ctrlr_lock must be held when calling this function.
3530 : : */
3531 : : static void
3532 : 9 : nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
3533 : : {
3534 : : struct nvme_request *req, *tmp_req;
3535 : : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3536 : : struct spdk_nvme_ctrlr_aer_completion *event;
3537 : :
3538 [ - + # # : 9 : STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
# # # # #
# # # # #
# # ]
3539 [ # # # # : 0 : STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
3540 : :
3541 [ # # # # : 0 : assert(req->pid == proc->pid);
# # # # #
# # # ]
3542 : 0 : nvme_cleanup_user_req(req);
3543 : 0 : nvme_free_request(req);
3544 : 0 : }
3545 : :
3546 : : /* Remove async event from each process objects event list */
3547 [ - + # # : 9 : while (!STAILQ_EMPTY(&proc->async_events)) {
# # # # ]
3548 [ # # # # : 0 : event = STAILQ_FIRST(&proc->async_events);
# # ]
3549 [ # # # # : 0 : STAILQ_REMOVE_HEAD(&proc->async_events, link);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
3550 : 0 : spdk_free(event);
3551 : : }
3552 : :
3553 [ - + # # : 9 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
# # # # #
# # # # #
# # ]
3554 [ # # # # : 0 : TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3555 : :
3556 : : /*
3557 : : * The process may have been killed while some qpairs were in their
3558 : : * completion context. Clear that flag here to allow these IO
3559 : : * qpairs to be deleted.
3560 : : */
3561 [ # # ]: 0 : qpair->in_completion_context = 0;
3562 : :
3563 [ # # ]: 0 : qpair->no_deletion_notification_needed = 1;
3564 : :
3565 : 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3566 : 0 : }
3567 : :
3568 : 9 : spdk_free(proc);
3569 : 9 : }
3570 : :
3571 : : /**
3572 : : * This function will be called when destructing the controller.
3573 : : * 1. There is no more admin request on this controller.
3574 : : * 2. Clean up any left resource allocation when its associated process is gone.
3575 : : */
3576 : : void
3577 : 3485 : nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
3578 : : {
3579 : : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3580 : :
3581 : : /* Free all the processes' properties and make sure no pending admin IOs */
3582 [ + + + - : 6815 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
+ - + + +
- + - + -
+ + ]
3583 [ + + + - : 3330 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
+ - - + #
# # # # #
# # # # #
# # # # #
# # + - +
- + - + -
+ - + - +
- + - + -
+ - + - +
- + - ]
3584 : :
3585 [ + + + - : 3330 : assert(STAILQ_EMPTY(&active_proc->active_reqs));
+ - + - #
# ]
3586 : :
3587 : 3330 : spdk_free(active_proc);
3588 : 817 : }
3589 : 3485 : }
3590 : :
3591 : : /**
3592 : : * This function will be called when any other process attaches or
3593 : : * detaches the controller in order to cleanup those unexpectedly
3594 : : * terminated processes.
3595 : : * Note: the ctrlr_lock must be held when calling this function.
3596 : : */
3597 : : static int
3598 : 10150 : nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
3599 : : {
3600 : : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3601 : 10150 : int active_proc_count = 0;
3602 : :
3603 [ + + + - : 21203 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
+ - + + +
- + - + -
+ + ]
3604 [ + + + - : 11053 : if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
- + # # #
# ]
3605 [ - + # # : 9 : NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid);
# # # # #
# # # # #
# # # # #
# # # #
# ]
3606 : :
3607 [ + - # # : 9 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# # # ]
3608 : :
3609 : 9 : nvme_ctrlr_cleanup_process(active_proc);
3610 : 0 : } else {
3611 [ + - ]: 11044 : active_proc_count++;
3612 : : }
3613 : 2451 : }
3614 : :
3615 : 10150 : return active_proc_count;
3616 : : }
3617 : :
3618 : : void
3619 : 3392 : nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
3620 : : {
3621 : : struct spdk_nvme_ctrlr_process *active_proc;
3622 : :
3623 : 3392 : nvme_ctrlr_lock(ctrlr);
3624 : :
3625 : 3392 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3626 : :
3627 : 3392 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3628 [ + - ]: 3392 : if (active_proc) {
3629 [ + - + - ]: 3392 : active_proc->ref++;
3630 : 817 : }
3631 : :
3632 : 3392 : nvme_ctrlr_unlock(ctrlr);
3633 : 3392 : }
3634 : :
3635 : : void
3636 : 3379 : nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
3637 : : {
3638 : : struct spdk_nvme_ctrlr_process *active_proc;
3639 : : int proc_count;
3640 : :
3641 : 3379 : nvme_ctrlr_lock(ctrlr);
3642 : :
3643 : 3379 : proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
3644 : :
3645 : 3379 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3646 [ + + ]: 3379 : if (active_proc) {
3647 [ + - + - ]: 3379 : active_proc->ref--;
3648 [ + + + - : 3379 : assert(active_proc->ref >= 0);
+ - # # ]
3649 : :
3650 : : /*
3651 : : * The last active process will be removed at the end of
3652 : : * the destruction of the controller.
3653 : : */
3654 [ + - + + : 3379 : if (active_proc->ref == 0 && proc_count != 1) {
+ - + - ]
3655 : 225 : nvme_ctrlr_remove_process(ctrlr, active_proc);
3656 : 0 : }
3657 : 817 : }
3658 : :
3659 : 3379 : nvme_ctrlr_unlock(ctrlr);
3660 : 3379 : }
3661 : :
3662 : : int
3663 : 3379 : nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
3664 : : {
3665 : : struct spdk_nvme_ctrlr_process *active_proc;
3666 : 3379 : int ref = 0;
3667 : :
3668 : 3379 : nvme_ctrlr_lock(ctrlr);
3669 : :
3670 : 3379 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3671 : :
3672 [ + + + - : 7053 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
+ - + + +
- + - +
- ]
3673 [ + - + - : 3674 : ref += active_proc->ref;
+ - ]
3674 : 817 : }
3675 : :
3676 : 3379 : nvme_ctrlr_unlock(ctrlr);
3677 : :
3678 : 3379 : return ref;
3679 : : }
3680 : :
3681 : : /**
3682 : : * Get the PCI device handle which is only visible to its associated process.
3683 : : */
3684 : : struct spdk_pci_device *
3685 : 859 : nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
3686 : : {
3687 : : struct spdk_nvme_ctrlr_process *active_proc;
3688 : 859 : struct spdk_pci_device *devhandle = NULL;
3689 : :
3690 : 859 : nvme_ctrlr_lock(ctrlr);
3691 : :
3692 : 859 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3693 [ + - ]: 859 : if (active_proc) {
3694 [ + - + - ]: 859 : devhandle = active_proc->devhandle;
3695 : 2 : }
3696 : :
3697 : 859 : nvme_ctrlr_unlock(ctrlr);
3698 : :
3699 : 859 : return devhandle;
3700 : : }
3701 : :
3702 : : static void
3703 : 3460 : nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3704 : : {
3705 : 3460 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3706 : :
3707 [ + - + + : 3460 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3708 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n");
# # # # #
# # # # #
# # # # #
# ]
3709 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3710 : 0 : return;
3711 : : }
3712 : :
3713 [ + + # # ]: 3460 : assert(value <= UINT32_MAX);
3714 [ + - + - : 3460 : ctrlr->vs.raw = (uint32_t)value;
+ - ]
3715 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
3716 : 817 : }
3717 : :
3718 : : static void
3719 : 3460 : nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3720 : : {
3721 : 3460 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3722 : :
3723 [ + - + + : 3460 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
+ - ]
3724 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
# # # # #
# # # # #
# # # # #
# ]
3725 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3726 : 0 : return;
3727 : : }
3728 : :
3729 [ + - + - : 3460 : ctrlr->cap.raw = value;
+ - ]
3730 : 3460 : nvme_ctrlr_init_cap(ctrlr);
3731 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
3732 : 817 : }
3733 : :
3734 : : static void
3735 : 3549 : nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3736 : : {
3737 : 3549 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3738 : : enum nvme_ctrlr_state state;
3739 : :
3740 [ + - + + : 3549 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3741 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# ]
3742 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3743 : 0 : return;
3744 : : }
3745 : :
3746 [ + + # # ]: 3549 : assert(value <= UINT32_MAX);
3747 [ + - + - : 3549 : ctrlr->process_init_cc.raw = (uint32_t)value;
+ - ]
3748 : :
3749 [ + + + - : 3549 : if (ctrlr->process_init_cc.bits.en) {
+ - - + ]
3750 [ - + - + : 678 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
3751 : 678 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1;
3752 : 0 : } else {
3753 : 2871 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0;
3754 : : }
3755 : :
3756 : 3549 : nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr));
3757 : 817 : }
3758 : :
3759 : : static void
3760 : 678 : nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3761 : : {
3762 : 678 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3763 : :
3764 [ + - - + : 678 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
3765 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n");
# # # # #
# # # # #
# # # # #
# ]
3766 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3767 : 0 : return;
3768 : : }
3769 : :
3770 : : /*
3771 : : * Wait 2.5 seconds before accessing PCI registers.
3772 : : * Not using sleep() to avoid blocking other controller's initialization.
3773 : : */
3774 [ - + # # : 678 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
# # ]
3775 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3776 [ # # # # : 0 : ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000);
# # ]
3777 : 0 : }
3778 : :
3779 : 678 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3780 : 0 : nvme_ctrlr_get_ready_timeout(ctrlr));
3781 : 0 : }
3782 : :
3783 : : static void
3784 : 678 : nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3785 : : {
3786 : 678 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3787 : : union spdk_nvme_cc_register cc;
3788 : : int rc;
3789 : :
3790 [ + - - + : 678 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
3791 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
# # # # #
# # # # #
# # # # #
# ]
3792 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3793 : 0 : return;
3794 : : }
3795 : :
3796 [ - + # # ]: 678 : assert(value <= UINT32_MAX);
3797 : 678 : cc.raw = (uint32_t)value;
3798 : 678 : cc.bits.en = 0;
3799 [ # # # # : 678 : ctrlr->process_init_cc.raw = cc.raw;
# # ]
3800 : :
3801 : 678 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC,
3802 : 0 : nvme_ctrlr_get_ready_timeout(ctrlr));
3803 : :
3804 : 678 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr);
3805 [ - + ]: 678 : if (rc != 0) {
3806 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
# # # # #
# # # # #
# # # # #
# ]
3807 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3808 : 0 : }
3809 : 0 : }
3810 : :
3811 : : static void
3812 : 678 : nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3813 : : {
3814 : 678 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3815 : : union spdk_nvme_csts_register csts;
3816 : :
3817 [ + - - + : 678 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
3818 : : /* While a device is resetting, it may be unable to service MMIO reads
3819 : : * temporarily. Allow for this case.
3820 : : */
3821 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # # # #
# # # #
# ]
3822 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3823 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3824 : : NVME_TIMEOUT_KEEP_EXISTING);
3825 : 0 : } else {
3826 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# ]
3827 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3828 : : }
3829 : :
3830 : 0 : return;
3831 : : }
3832 : :
3833 [ - + # # ]: 678 : assert(value <= UINT32_MAX);
3834 : 678 : csts.raw = (uint32_t)value;
3835 [ - + - - ]: 678 : if (csts.bits.rdy == 1 || csts.bits.cfs == 1) {
3836 : 678 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0,
3837 : 0 : nvme_ctrlr_get_ready_timeout(ctrlr));
3838 : 0 : } else {
3839 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3840 : 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3841 : : NVME_TIMEOUT_KEEP_EXISTING);
3842 : : }
3843 : 0 : }
3844 : :
3845 : : static void
3846 : 4355 : nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3847 : : {
3848 : 4355 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3849 : : union spdk_nvme_csts_register csts;
3850 : :
3851 [ + - + + : 4355 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3852 : : /* While a device is resetting, it may be unable to service MMIO reads
3853 : : * temporarily. Allow for this case.
3854 : : */
3855 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # # # #
# # # #
# ]
3856 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3857 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3858 : : NVME_TIMEOUT_KEEP_EXISTING);
3859 : 0 : } else {
3860 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# ]
3861 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3862 : : }
3863 : :
3864 : 0 : return;
3865 : : }
3866 : :
3867 [ + + # # ]: 4355 : assert(value <= UINT32_MAX);
3868 : 4355 : csts.raw = (uint32_t)value;
3869 [ + + ]: 4355 : if (csts.bits.rdy == 0) {
3870 [ + + + + : 3549 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n");
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
3871 : 4366 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED,
3872 : 817 : nvme_ctrlr_get_ready_timeout(ctrlr));
3873 : 817 : } else {
3874 : 806 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3875 : : NVME_TIMEOUT_KEEP_EXISTING);
3876 : : }
3877 : 817 : }
3878 : :
3879 : : static void
3880 : 34916 : nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
3881 : : const struct spdk_nvme_cpl *cpl)
3882 : : {
3883 : 34916 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3884 : : union spdk_nvme_csts_register csts;
3885 : :
3886 [ + - + + : 34916 : if (spdk_nvme_cpl_is_error(cpl)) {
+ - + - +
- + - + -
- + ]
3887 : : /* While a device is resetting, it may be unable to service MMIO reads
3888 : : * temporarily. Allow for this case.
3889 : : */
3890 [ # # # # : 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
# # # # #
# # # #
# ]
3891 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
3892 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3893 : : NVME_TIMEOUT_KEEP_EXISTING);
3894 : 0 : } else {
3895 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
# # # # #
# # # # #
# # # # #
# ]
3896 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3897 : : }
3898 : :
3899 : 0 : return;
3900 : : }
3901 : :
3902 [ + + # # ]: 34916 : assert(value <= UINT32_MAX);
3903 : 34916 : csts.raw = value;
3904 [ + + ]: 34916 : if (csts.bits.rdy == 1) {
3905 [ + + + + : 3424 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
3906 : : /*
3907 : : * The controller has been enabled.
3908 : : * Perform the rest of initialization serially.
3909 : : */
3910 : 4241 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3911 [ + - + - : 3424 : ctrlr->opts.admin_timeout_ms);
+ - ]
3912 : 817 : } else {
3913 : 31492 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3914 : : NVME_TIMEOUT_KEEP_EXISTING);
3915 : : }
3916 : 3804 : }
3917 : :
3918 : : /**
3919 : : * This function will be called repeatedly during initialization until the controller is ready.
3920 : : */
3921 : : int
3922 : 151963622 : nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
3923 : : {
3924 : : uint32_t ready_timeout_in_ms;
3925 : : uint64_t ticks;
3926 : 151963622 : int rc = 0;
3927 : :
3928 : 151963622 : ticks = spdk_get_ticks();
3929 : :
3930 : : /*
3931 : : * May need to avoid accessing any register on the target controller
3932 : : * for a while. Return early without touching the FSM.
3933 : : * Check sleep_timeout_tsc > 0 for unit test.
3934 : : */
3935 [ + + + - : 182455463 : if ((ctrlr->sleep_timeout_tsc > 0) &&
+ + + + ]
3936 [ + + + - ]: 146129044 : (ticks <= ctrlr->sleep_timeout_tsc)) {
3937 : 146128939 : return 0;
3938 : : }
3939 [ + - + - ]: 5834683 : ctrlr->sleep_timeout_tsc = 0;
3940 : :
3941 : 5834683 : ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr);
3942 : :
3943 : : /*
3944 : : * Check if the current initialization step is done or has timed out.
3945 : : */
3946 [ + - + + : 5834683 : switch (ctrlr->state) {
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + -
- ]
3947 : 719 : case NVME_CTRLR_STATE_INIT_DELAY:
3948 : 721 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3949 [ + + + - : 721 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
- + ]
3950 : : /*
3951 : : * Controller may need some delay before it's enabled.
3952 : : *
3953 : : * This is a workaround for an issue where the PCIe-attached NVMe controller
3954 : : * is not ready after VFIO reset. We delay the initialization rather than the
3955 : : * enabling itself, because this is required only for the very first enabling
3956 : : * - directly after a VFIO reset.
3957 : : */
3958 [ + + + + : 105 : NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n");
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
3959 [ + - + - : 105 : ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
+ - ]
3960 : 2 : }
3961 : 721 : break;
3962 : :
3963 : 0 : case NVME_CTRLR_STATE_DISCONNECTED:
3964 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3965 : 0 : break;
3966 : :
3967 : 3059 : case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */
3968 [ + - + - ]: 3876 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
3969 [ + - ]: 3876 : if (rc == 0) {
3970 : 3876 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ,
3971 : : NVME_TIMEOUT_INFINITE);
3972 : 817 : } else {
3973 : 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3974 : : }
3975 : 3876 : break;
3976 : :
3977 : 2057433 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
3978 [ + - + - ]: 2438944 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3979 : :
3980 [ + + + + : 2438944 : switch (nvme_qpair_get_state(ctrlr->adminq)) {
+ - + + -
- ]
3981 : 1130998 : case NVME_QPAIR_CONNECTING:
3982 [ + + + + : 1511692 : if (ctrlr->is_failed) {
+ - - + ]
3983 [ # # # # ]: 0 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
3984 : 0 : break;
3985 : : }
3986 : :
3987 : 1511692 : break;
3988 : 1858 : case NVME_QPAIR_CONNECTED:
3989 [ - + - + ]: 2666 : nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
3990 : : /* Fall through */
3991 : 2643 : case NVME_QPAIR_ENABLED:
3992 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS,
3993 : : NVME_TIMEOUT_INFINITE);
3994 : : /* Abort any queued requests that were sent while the adminq was connecting
3995 : : * to avoid stalling the init process during a reset, as requests don't get
3996 : : * resubmitted while the controller is resetting and subsequent commands
3997 : : * would get queued too.
3998 : : */
3999 [ + - + - ]: 3460 : nvme_qpair_abort_queued_reqs(ctrlr->adminq);
4000 : 3460 : break;
4001 : 923376 : case NVME_QPAIR_DISCONNECTING:
4002 [ - + # # : 923376 : assert(ctrlr->adminq->async == true);
# # # # #
# ]
4003 : 923376 : break;
4004 : 416 : case NVME_QPAIR_DISCONNECTED:
4005 : : /* fallthrough */
4006 : : default:
4007 : 416 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4008 : 416 : break;
4009 : : }
4010 : :
4011 : 2438944 : break;
4012 : :
4013 : 2643 : case NVME_CTRLR_STATE_READ_VS:
4014 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE);
4015 : 3460 : rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr);
4016 : 3460 : break;
4017 : :
4018 : 2643 : case NVME_CTRLR_STATE_READ_CAP:
4019 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
4020 : 3460 : rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
4021 : 3460 : break;
4022 : :
4023 : 2732 : case NVME_CTRLR_STATE_CHECK_EN:
4024 : : /* Begin the hardware initialization by making sure the controller is disabled. */
4025 : 3549 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms);
4026 : 3549 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr);
4027 : 3549 : break;
4028 : :
4029 : 678 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
4030 : : /*
4031 : : * Controller is currently enabled. We need to disable it to cause a reset.
4032 : : *
4033 : : * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
4034 : : * Wait for the ready bit to be 1 before disabling the controller.
4035 : : */
4036 : 678 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
4037 : : NVME_TIMEOUT_KEEP_EXISTING);
4038 : 678 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
4039 : 678 : break;
4040 : :
4041 : 678 : case NVME_CTRLR_STATE_SET_EN_0:
4042 [ - + - + : 678 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
4043 : 678 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms);
4044 : 678 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr);
4045 : 678 : break;
4046 : :
4047 : 3538 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
4048 : 4355 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
4049 : : NVME_TIMEOUT_KEEP_EXISTING);
4050 : 4355 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
4051 : 4355 : break;
4052 : :
4053 : 2729 : case NVME_CTRLR_STATE_DISABLED:
4054 [ + + + + : 3546 : if (ctrlr->is_disconnecting) {
+ - - + ]
4055 [ - + - + : 86 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n");
- - # # #
# # # # #
# # # # #
# # # # #
# # ]
4056 : 0 : } else {
4057 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
4058 : :
4059 : : /*
4060 : : * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
4061 : : * set to 1 if it is too soon after CSTS.RDY is reported as 0.
4062 : : */
4063 : 3460 : spdk_delay_us(100);
4064 : : }
4065 : 3546 : break;
4066 : :
4067 : 2643 : case NVME_CTRLR_STATE_ENABLE:
4068 [ + + + + : 3460 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n");
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
4069 : 3460 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms);
4070 : 3460 : rc = nvme_ctrlr_enable(ctrlr);
4071 [ + + ]: 3460 : if (rc) {
4072 [ - + # # : 21 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc);
# # # # #
# # # # #
# # # # #
# ]
4073 : 0 : }
4074 : 3460 : return rc;
4075 : :
4076 : 31112 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
4077 : 34916 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
4078 : : NVME_TIMEOUT_KEEP_EXISTING);
4079 : 34916 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
4080 : : ctrlr);
4081 : 34916 : break;
4082 : :
4083 : 2607 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
4084 [ - + - + ]: 3424 : nvme_transport_qpair_reset(ctrlr->adminq);
4085 : 3424 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
4086 : 3424 : break;
4087 : :
4088 : 2628 : case NVME_CTRLR_STATE_IDENTIFY:
4089 : 3445 : rc = nvme_ctrlr_identify(ctrlr);
4090 : 3445 : break;
4091 : :
4092 : 2637 : case NVME_CTRLR_STATE_CONFIGURE_AER:
4093 : 3454 : rc = nvme_ctrlr_configure_aer(ctrlr);
4094 : 3454 : break;
4095 : :
4096 : 2646 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
4097 : 3463 : rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
4098 : 3463 : break;
4099 : :
4100 : 2485 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
4101 : 3302 : rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
4102 : 3302 : break;
4103 : :
4104 : 987 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
4105 : 987 : rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
4106 : 987 : break;
4107 : :
4108 : 2485 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
4109 : 3302 : nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
4110 : 3302 : rc = nvme_ctrlr_set_num_queues(ctrlr);
4111 : 3302 : break;
4112 : :
4113 : 2500 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
4114 : 3317 : _nvme_ctrlr_identify_active_ns(ctrlr);
4115 : 3317 : break;
4116 : :
4117 : 2470 : case NVME_CTRLR_STATE_IDENTIFY_NS:
4118 : 3287 : rc = nvme_ctrlr_identify_namespaces(ctrlr);
4119 : 3287 : break;
4120 : :
4121 : 2470 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
4122 : 3287 : rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
4123 : 3287 : break;
4124 : :
4125 : 2470 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
4126 : 3287 : rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
4127 : 3287 : break;
4128 : :
4129 : 2473 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
4130 : 3290 : rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
4131 : 3290 : break;
4132 : :
4133 : 121 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
4134 : 123 : rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
4135 : 123 : break;
4136 : :
4137 : 2470 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
4138 : 3287 : nvme_ctrlr_set_supported_features(ctrlr);
4139 : 4104 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_FEATURE,
4140 [ + - + - : 3287 : ctrlr->opts.admin_timeout_ms);
+ - ]
4141 : 3287 : break;
4142 : :
4143 : 2476 : case NVME_CTRLR_STATE_SET_HOST_FEATURE:
4144 : 3293 : rc = nvme_ctrlr_set_host_feature(ctrlr);
4145 : 3293 : break;
4146 : :
4147 : 2470 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
4148 : 3287 : rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
4149 : 3287 : break;
4150 : :
4151 : 2470 : case NVME_CTRLR_STATE_SET_HOST_ID:
4152 : 3287 : rc = nvme_ctrlr_set_host_id(ctrlr);
4153 : 3287 : break;
4154 : :
4155 : 2479 : case NVME_CTRLR_STATE_TRANSPORT_READY:
4156 : 3296 : rc = nvme_transport_ctrlr_ready(ctrlr);
4157 [ + + ]: 3296 : if (rc) {
4158 [ - + # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc);
# # # # #
# # # # #
# # # # #
# ]
4159 : 3 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4160 : 0 : } else {
4161 : 3293 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
4162 : : }
4163 : 3296 : break;
4164 : :
4165 : 41 : case NVME_CTRLR_STATE_READY:
4166 [ - + + + : 41 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n");
+ - # # #
# # # # #
# # # # #
# # # # #
# # ]
4167 : 41 : return 0;
4168 : :
4169 : 439 : case NVME_CTRLR_STATE_ERROR:
4170 [ + - # # : 439 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n");
# # # # #
# # # # #
# # # # #
# ]
4171 : 439 : return -1;
4172 : :
4173 : 3100508 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
4174 : : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
4175 : : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
4176 : : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
4177 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4178 : : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
4179 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
4180 : : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4181 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
4182 : : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
4183 : : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
4184 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
4185 : : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
4186 : : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
4187 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
4188 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
4189 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
4190 : : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
4191 : : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
4192 : : case NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE:
4193 : : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
4194 : : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
4195 : : /*
4196 : : * nvme_ctrlr_process_init() may be called from the completion context
4197 : : * for the admin qpair. Avoid recursive calls for this case.
4198 : : */
4199 [ + + + - : 3278142 : if (!ctrlr->adminq->in_completion_context) {
+ - - + ]
4200 [ + - + - ]: 3278056 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4201 : 177634 : }
4202 : 3278142 : break;
4203 : :
4204 : 0 : default:
4205 [ # # ]: 0 : assert(0);
4206 : : return -1;
4207 : : }
4208 : :
4209 [ + + ]: 5830743 : if (rc) {
4210 [ - + # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
4211 : : rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4212 : 0 : }
4213 : :
4214 : : /* Note: we use the ticks captured when we entered this function.
4215 : : * This covers environments where the SPDK process gets swapped out after
4216 : : * we tried to advance the state but before we check the timeout here.
4217 : : * It is not normal for this to happen, but harmless to handle it in this
4218 : : * way.
4219 : : */
4220 [ + + + - : 6010464 : if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
+ + + - ]
4221 [ + + + - ]: 3229173 : ticks > ctrlr->state_timeout_tsc) {
4222 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # # # ]
4223 : : ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4224 : 0 : return -1;
4225 : : }
4226 : :
4227 : 5830743 : return rc;
4228 : 31073583 : }
4229 : :
4230 : : int
4231 : 3480 : nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
4232 : : {
4233 : 566 : pthread_mutexattr_t attr;
4234 : 3480 : int rc = 0;
4235 : :
4236 [ + + - + ]: 3480 : if (pthread_mutexattr_init(&attr)) {
4237 : 0 : return -1;
4238 : : }
4239 [ + + + - : 6960 : if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
+ + ]
4240 : : #ifndef __FreeBSD__
4241 [ + + + - ]: 6143 : pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
4242 [ + + + + ]: 6143 : pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
4243 : : #endif
4244 [ + + ]: 3480 : pthread_mutex_init(mtx, &attr)) {
4245 : 0 : rc = -1;
4246 : 0 : }
4247 [ + + ]: 3480 : pthread_mutexattr_destroy(&attr);
4248 : 3480 : return rc;
4249 : 817 : }
4250 : :
4251 : : int
4252 : 3480 : nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
4253 : : {
4254 : : int rc;
4255 : :
4256 [ + + + - : 3480 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
+ - + + ]
4257 : 721 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
4258 : 2 : } else {
4259 : 2759 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
4260 : : }
4261 : :
4262 [ + + + - : 3480 : if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
+ - + - ]
4263 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
4264 : : ctrlr->opts.admin_queue_size);
4265 [ # # # # : 0 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
# # ]
4266 : 0 : }
4267 : :
4268 [ + + + - : 3480 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE &&
- + # # ]
4269 [ # # # # : 0 : (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) {
# # # # ]
4270 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr,
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
4271 : : "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n",
4272 : : ctrlr->opts.admin_queue_size);
4273 [ # # # # : 0 : ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size,
# # # # #
# # # #
# ]
4274 : : SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE);
4275 : 0 : }
4276 : :
4277 [ + + + - : 3480 : if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
+ - + - ]
4278 [ + + # # : 78 : NVME_CTRLR_ERRLOG(ctrlr,
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
4279 : : "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
4280 : : ctrlr->opts.admin_queue_size);
4281 [ # # # # : 78 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
# # ]
4282 : 0 : }
4283 : :
4284 [ + - + - ]: 3480 : ctrlr->flags = 0;
4285 [ + - + - ]: 3480 : ctrlr->free_io_qids = NULL;
4286 [ + - + - ]: 3480 : ctrlr->is_resetting = false;
4287 [ + - + - ]: 3480 : ctrlr->is_failed = false;
4288 [ + - + - ]: 3480 : ctrlr->is_destructed = false;
4289 : :
4290 [ + - + - : 3480 : TAILQ_INIT(&ctrlr->active_io_qpairs);
+ - + - +
- + - + -
+ - ]
4291 [ + - + - : 3480 : STAILQ_INIT(&ctrlr->queued_aborts);
+ - + - +
- + - + -
+ - ]
4292 [ + - + - ]: 3480 : ctrlr->outstanding_aborts = 0;
4293 : :
4294 [ + - + - ]: 3480 : ctrlr->ana_log_page = NULL;
4295 [ + - + - ]: 3480 : ctrlr->ana_log_page_size = 0;
4296 : :
4297 [ + - ]: 3480 : rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
4298 [ - + ]: 3480 : if (rc != 0) {
4299 : 0 : return rc;
4300 : : }
4301 : :
4302 [ + - + - : 3480 : TAILQ_INIT(&ctrlr->active_procs);
+ - + - +
- + - + -
+ - ]
4303 [ + - + - : 3480 : STAILQ_INIT(&ctrlr->register_operations);
+ - + - +
- + - + -
+ - ]
4304 : :
4305 [ + - + - : 3480 : RB_INIT(&ctrlr->ns);
+ - ]
4306 : :
4307 : 3480 : return rc;
4308 : 817 : }
4309 : :
4310 : : static void
4311 : 3460 : nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
4312 : : {
4313 [ + + + - : 3460 : if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
+ - + + ]
4314 [ + - + - ]: 152 : ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
4315 : 2 : }
4316 : :
4317 [ + + + - : 3460 : ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
+ - + - +
- + - +
- ]
4318 : :
4319 : : /* For now, always select page_size == min_page_size. */
4320 [ + - + - : 3460 : ctrlr->page_size = ctrlr->min_page_size;
+ - + - ]
4321 : :
4322 [ + - + - : 3460 : ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
+ - + - +
- + - + -
+ - + - +
- ]
4323 [ + - + - : 3460 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
+ - + - +
- + - + -
+ - # # +
- + - +
- ]
4324 [ + + + - : 3462 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE &&
+ + - + ]
4325 [ + + + - : 115 : ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) {
+ - ]
4326 : : /* If the user specifically set an IO queue size different than the
4327 : : * default, use that value. Otherwise overwrite with the quirked value.
4328 : : * This allows this quirk to be overridden when necessary.
4329 : : * However, cap.mqes still needs to be respected.
4330 : : */
4331 [ + - + - : 103 : ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK;
+ - ]
4332 : 2 : }
4333 [ + - + - : 3460 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
+ - + - +
- + - + +
+ - + - +
- + - + -
+ - + - +
- + - ]
4334 : :
4335 [ + - + - : 3460 : ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
+ - + - +
- + - + +
+ - + - +
- + - + -
+ - + - +
- + - ]
4336 : 3460 : }
4337 : :
4338 : : void
4339 : 3476 : nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
4340 : : {
4341 : : int rc;
4342 : :
4343 [ + + + - : 3476 : if (ctrlr->lock_depth > 0) {
+ - ]
4344 [ # # # # ]: 0 : SPDK_ERRLOG("lock currently held (depth=%d)!\n", ctrlr->lock_depth);
4345 [ # # ]: 0 : assert(false);
4346 : : }
4347 : :
4348 [ + + + - ]: 3476 : rc = pthread_mutex_destroy(&ctrlr->ctrlr_lock);
4349 [ + + ]: 3476 : if (rc) {
4350 : 0 : SPDK_ERRLOG("could not destroy ctrlr_lock: %s\n", spdk_strerror(rc));
4351 [ # # ]: 0 : assert(false);
4352 : : }
4353 : :
4354 : 3476 : nvme_ctrlr_free_processes(ctrlr);
4355 : 3476 : }
4356 : :
4357 : : void
4358 : 3462 : nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
4359 : : struct nvme_ctrlr_detach_ctx *ctx)
4360 : : {
4361 : : struct spdk_nvme_qpair *qpair, *tmp;
4362 : :
4363 [ + + + + : 3462 : NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n");
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
4364 : :
4365 [ + - + - ]: 3462 : ctrlr->prepare_for_reset = false;
4366 [ + - + - ]: 3462 : ctrlr->is_destructed = true;
4367 : :
4368 [ + - + - ]: 3462 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4369 : :
4370 : 3462 : nvme_ctrlr_abort_queued_aborts(ctrlr);
4371 [ + - + - ]: 3462 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
4372 : :
4373 [ + + + - : 3760 : TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
+ - + + +
- + - + -
+ + ]
4374 : 298 : spdk_nvme_ctrlr_free_io_qpair(qpair);
4375 : 1 : }
4376 : :
4377 : 3462 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
4378 : 3462 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
4379 : :
4380 : 3462 : nvme_ctrlr_shutdown_async(ctrlr, ctx);
4381 : 3462 : }
4382 : :
4383 : : int
4384 : 20243968 : nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
4385 : : struct nvme_ctrlr_detach_ctx *ctx)
4386 : : {
4387 : : struct spdk_nvme_ns *ns, *tmp_ns;
4388 : 20243968 : int rc = 0;
4389 : :
4390 [ + + + + : 20243968 : if (!ctx->shutdown_complete) {
+ - - + ]
4391 : 20243738 : rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
4392 [ + + ]: 20243738 : if (rc == -EAGAIN) {
4393 : 20240506 : return -EAGAIN;
4394 : : }
4395 : : /* Destruct ctrlr forcefully for any other error. */
4396 : 817 : }
4397 : :
4398 [ + + + - : 3462 : if (ctx->cb_fn) {
+ - ]
4399 [ + - + - : 3154 : ctx->cb_fn(ctrlr);
- + + - ]
4400 : 817 : }
4401 : :
4402 [ + - + - ]: 3462 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
4403 : :
4404 [ + + + + : 29328 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
+ + ]
4405 [ + - + - ]: 25866 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
4406 [ + - ]: 25866 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
4407 : 25866 : spdk_free(ns);
4408 : 817 : }
4409 : :
4410 [ + - + - ]: 3462 : ctrlr->active_ns_count = 0;
4411 : :
4412 [ + - ]: 3462 : spdk_bit_array_free(&ctrlr->free_io_qids);
4413 : :
4414 [ + - + - ]: 3462 : free(ctrlr->ana_log_page);
4415 [ + - + - ]: 3462 : free(ctrlr->copied_ana_desc);
4416 [ + - + - ]: 3462 : ctrlr->ana_log_page = NULL;
4417 [ + - + - ]: 3462 : ctrlr->copied_ana_desc = NULL;
4418 [ + - + - ]: 3462 : ctrlr->ana_log_page_size = 0;
4419 : :
4420 : 3462 : nvme_transport_ctrlr_destruct(ctrlr);
4421 : :
4422 : 3462 : return rc;
4423 : 1194797 : }
4424 : :
4425 : : void
4426 : 308 : nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
4427 : : {
4428 : 308 : struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr };
4429 : : int rc;
4430 : :
4431 : 308 : nvme_ctrlr_destruct_async(ctrlr, &ctx);
4432 : :
4433 : 0 : while (1) {
4434 : 1154 : rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
4435 [ + + ]: 1154 : if (rc != -EAGAIN) {
4436 : 308 : break;
4437 : : }
4438 : 846 : nvme_delay(1000);
4439 : : }
4440 : 308 : }
4441 : :
4442 : : int
4443 : 1606064 : nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
4444 : : struct nvme_request *req)
4445 : : {
4446 [ + - + - ]: 1606064 : return nvme_qpair_submit_request(ctrlr->adminq, req);
4447 : : }
4448 : :
4449 : : static void
4450 : 2389 : nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
4451 : : {
4452 : : /* Do nothing */
4453 : 2389 : }
4454 : :
4455 : : /*
4456 : : * Check if we need to send a Keep Alive command.
4457 : : * Caller must hold ctrlr->ctrlr_lock.
4458 : : */
4459 : : static int
4460 : 6069424 : nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
4461 : : {
4462 : : uint64_t now;
4463 : : struct nvme_request *req;
4464 : : struct spdk_nvme_cmd *cmd;
4465 : 6069424 : int rc = 0;
4466 : :
4467 : 6069424 : now = spdk_get_ticks();
4468 [ + + + - : 6069424 : if (now < ctrlr->next_keep_alive_tick) {
+ + ]
4469 : 6035759 : return rc;
4470 : : }
4471 : :
4472 [ + - + - ]: 33665 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
4473 [ + + ]: 33665 : if (req == NULL) {
4474 : 31269 : return rc;
4475 : : }
4476 : :
4477 [ + - ]: 2396 : cmd = &req->cmd;
4478 [ + - ]: 2396 : cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
4479 : :
4480 : 2396 : rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
4481 [ + + ]: 2396 : if (rc != 0) {
4482 [ + - # # : 7 : NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n");
# # # # #
# # # # #
# # # # #
# ]
4483 : 7 : rc = -ENXIO;
4484 : 0 : }
4485 : :
4486 [ + - + - : 2396 : ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
+ - + - ]
4487 : 2396 : return rc;
4488 : 10275 : }
4489 : :
4490 : : int32_t
4491 : 50456413 : spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
4492 : : {
4493 : : int32_t num_completions;
4494 : : int32_t rc;
4495 : : struct spdk_nvme_ctrlr_process *active_proc;
4496 : :
4497 : 50456413 : nvme_ctrlr_lock(ctrlr);
4498 : :
4499 [ + + + - : 50456413 : if (ctrlr->keep_alive_interval_ticks) {
+ + ]
4500 : 6069424 : rc = nvme_ctrlr_keep_alive(ctrlr);
4501 [ + + ]: 6069424 : if (rc) {
4502 : 7 : nvme_ctrlr_unlock(ctrlr);
4503 : 7 : return rc;
4504 : : }
4505 : 10275 : }
4506 : :
4507 : 50456406 : rc = nvme_io_msg_process(ctrlr);
4508 [ + + ]: 50456406 : if (rc < 0) {
4509 : 0 : nvme_ctrlr_unlock(ctrlr);
4510 : 0 : return rc;
4511 : : }
4512 : 50456406 : num_completions = rc;
4513 : :
4514 [ + - + - ]: 50456406 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4515 : :
4516 : : /* Each process has an async list, complete the ones for this process object */
4517 : 50456406 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4518 [ + + ]: 50456406 : if (active_proc) {
4519 : 50456403 : nvme_ctrlr_complete_queued_async_events(ctrlr);
4520 : 10301 : }
4521 : :
4522 [ + + + + : 50456406 : if (rc == -ENXIO && ctrlr->is_disconnecting) {
+ + # # #
# ]
4523 : 514 : nvme_ctrlr_disconnect_done(ctrlr);
4524 : 0 : }
4525 : :
4526 : 50456406 : nvme_ctrlr_unlock(ctrlr);
4527 : :
4528 [ + + ]: 50456406 : if (rc < 0) {
4529 : 1301 : num_completions = rc;
4530 : 0 : } else {
4531 [ + - ]: 50455105 : num_completions += rc;
4532 : : }
4533 : :
4534 : 50456406 : return num_completions;
4535 : 10301 : }
4536 : :
4537 : : const struct spdk_nvme_ctrlr_data *
4538 : 2491227 : spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
4539 : : {
4540 [ + - ]: 2491227 : return &ctrlr->cdata;
4541 : : }
4542 : :
4543 : 32517 : union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
4544 : : {
4545 : 21449 : union spdk_nvme_csts_register csts;
4546 : :
4547 [ - + ]: 32517 : if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
4548 : 0 : csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4549 : 0 : }
4550 : 32517 : return csts;
4551 : : }
4552 : :
4553 : 0 : union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr)
4554 : : {
4555 : 0 : union spdk_nvme_cc_register cc;
4556 : :
4557 [ # # ]: 0 : if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
4558 : 0 : cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4559 : 0 : }
4560 : 0 : return cc;
4561 : : }
4562 : :
4563 : 94 : union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
4564 : : {
4565 [ # # ]: 94 : return ctrlr->cap;
4566 : : }
4567 : :
4568 : 1202 : union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
4569 : : {
4570 [ # # ]: 1202 : return ctrlr->vs;
4571 : : }
4572 : :
4573 : 8 : union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
4574 : : {
4575 : 0 : union spdk_nvme_cmbsz_register cmbsz;
4576 : :
4577 [ - + ]: 8 : if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
4578 : 0 : cmbsz.raw = 0;
4579 : 0 : }
4580 : :
4581 : 8 : return cmbsz;
4582 : : }
4583 : :
4584 : 8 : union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
4585 : : {
4586 : 0 : union spdk_nvme_pmrcap_register pmrcap;
4587 : :
4588 [ - + ]: 8 : if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
4589 : 0 : pmrcap.raw = 0;
4590 : 0 : }
4591 : :
4592 : 8 : return pmrcap;
4593 : : }
4594 : :
4595 : 0 : union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr)
4596 : : {
4597 : 0 : union spdk_nvme_bpinfo_register bpinfo;
4598 : :
4599 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
4600 : 0 : bpinfo.raw = 0;
4601 : 0 : }
4602 : :
4603 : 0 : return bpinfo;
4604 : : }
4605 : :
4606 : : uint64_t
4607 : 8 : spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr)
4608 : : {
4609 [ # # # # ]: 8 : return ctrlr->pmr_size;
4610 : : }
4611 : :
4612 : : uint32_t
4613 : 33 : spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
4614 : : {
4615 [ + - + - : 33 : return ctrlr->cdata.nn;
+ - ]
4616 : : }
4617 : :
4618 : : bool
4619 : 28032 : spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4620 : : {
4621 : 27943 : struct spdk_nvme_ns tmp, *ns;
4622 : :
4623 [ # # ]: 28032 : tmp.id = nsid;
4624 [ # # ]: 28032 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4625 : :
4626 [ + + ]: 28032 : if (ns != NULL) {
4627 [ - + # # : 27746 : return ns->active;
# # ]
4628 : : }
4629 : :
4630 : 286 : return false;
4631 : 0 : }
4632 : :
4633 : : uint32_t
4634 : 12433 : spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
4635 : : {
4636 : : struct spdk_nvme_ns *ns;
4637 : :
4638 [ + - ]: 12433 : ns = RB_MIN(nvme_ns_tree, &ctrlr->ns);
4639 [ + + ]: 12433 : if (ns == NULL) {
4640 : 1286 : return 0;
4641 : : }
4642 : :
4643 [ + + ]: 25034 : while (ns != NULL) {
4644 [ + + + + : 24990 : if (ns->active) {
+ - - + ]
4645 [ - + - + ]: 11103 : return ns->id;
4646 : : }
4647 : :
4648 : 13887 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4649 : : }
4650 : :
4651 : 44 : return 0;
4652 : 1641 : }
4653 : :
4654 : : uint32_t
4655 : 25661 : spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
4656 : : {
4657 : 15898 : struct spdk_nvme_ns tmp, *ns;
4658 : :
4659 [ + - ]: 25661 : tmp.id = prev_nsid;
4660 [ + - ]: 25661 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4661 [ + + ]: 25661 : if (ns == NULL) {
4662 : 15 : return 0;
4663 : : }
4664 : :
4665 : 25646 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4666 [ + + ]: 30244 : while (ns != NULL) {
4667 [ + + + + : 19231 : if (ns->active) {
# # # # ]
4668 [ # # # # ]: 14633 : return ns->id;
4669 : : }
4670 : :
4671 : 4598 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4672 : : }
4673 : :
4674 : 11013 : return 0;
4675 : 1633 : }
4676 : :
4677 : : struct spdk_nvme_ns *
4678 : 57078 : spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4679 : : {
4680 : 41066 : struct spdk_nvme_ns tmp;
4681 : : struct spdk_nvme_ns *ns;
4682 : :
4683 [ + + + + : 57078 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
+ - + - -
+ ]
4684 : 7397 : return NULL;
4685 : : }
4686 : :
4687 : 49681 : nvme_ctrlr_lock(ctrlr);
4688 : :
4689 [ + - ]: 49681 : tmp.id = nsid;
4690 [ + - ]: 49681 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4691 : :
4692 [ + + ]: 49681 : if (ns == NULL) {
4693 : 25874 : ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_NUMA_ID_ANY, SPDK_MALLOC_SHARE);
4694 [ + + ]: 25874 : if (ns == NULL) {
4695 : 0 : nvme_ctrlr_unlock(ctrlr);
4696 : 0 : return NULL;
4697 : : }
4698 : :
4699 [ + + + + : 25874 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid);
+ + # # #
# # # # #
# # # # #
# # # # #
# # ]
4700 [ + - + - ]: 25874 : ns->id = nsid;
4701 [ + - ]: 25874 : RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns);
4702 : 817 : }
4703 : :
4704 : 49681 : nvme_ctrlr_unlock(ctrlr);
4705 : :
4706 : 49681 : return ns;
4707 : 4090 : }
4708 : :
4709 : : struct spdk_pci_device *
4710 : 145 : spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
4711 : : {
4712 [ - + ]: 145 : if (ctrlr == NULL) {
4713 : 0 : return NULL;
4714 : : }
4715 : :
4716 [ - + # # : 145 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
# # # # ]
4717 : 0 : return NULL;
4718 : : }
4719 : :
4720 : 145 : return nvme_ctrlr_proc_get_devhandle(ctrlr);
4721 : 0 : }
4722 : :
4723 : : int32_t
4724 : 23801 : spdk_nvme_ctrlr_get_numa_id(struct spdk_nvme_ctrlr *ctrlr)
4725 : : {
4726 [ + + + - : 23801 : if (ctrlr->numa.id_valid) {
+ + ]
4727 [ - + - + ]: 16129 : return ctrlr->numa.id;
4728 : : } else {
4729 : 7672 : return SPDK_ENV_NUMA_ID_ANY;
4730 : : }
4731 : 19 : }
4732 : :
4733 : : uint16_t
4734 : 838 : spdk_nvme_ctrlr_get_id(struct spdk_nvme_ctrlr *ctrlr)
4735 : : {
4736 [ # # # # ]: 838 : return ctrlr->cntlid;
4737 : : }
4738 : :
4739 : : uint32_t
4740 : 1416 : spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
4741 : : {
4742 [ + - + - ]: 1416 : return ctrlr->max_xfer_size;
4743 : : }
4744 : :
4745 : : uint16_t
4746 : 1235 : spdk_nvme_ctrlr_get_max_sges(const struct spdk_nvme_ctrlr *ctrlr)
4747 : : {
4748 [ + - # # : 1235 : if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) {
# # ]
4749 [ # # # # ]: 1235 : return ctrlr->max_sges;
4750 : : } else {
4751 : 0 : return UINT16_MAX;
4752 : : }
4753 : 0 : }
4754 : :
4755 : : void
4756 : 1657 : spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
4757 : : spdk_nvme_aer_cb aer_cb_fn,
4758 : : void *aer_cb_arg)
4759 : : {
4760 : : struct spdk_nvme_ctrlr_process *active_proc;
4761 : :
4762 : 1657 : nvme_ctrlr_lock(ctrlr);
4763 : :
4764 : 1657 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4765 [ + - ]: 1657 : if (active_proc) {
4766 [ + - + - ]: 1657 : active_proc->aer_cb_fn = aer_cb_fn;
4767 [ + - + - ]: 1657 : active_proc->aer_cb_arg = aer_cb_arg;
4768 : 1 : }
4769 : :
4770 : 1657 : nvme_ctrlr_unlock(ctrlr);
4771 : 1657 : }
4772 : :
4773 : : void
4774 : 0 : spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr)
4775 : : {
4776 [ # # # # : 0 : ctrlr->opts.disable_read_changed_ns_list_log_page = true;
# # ]
4777 : 0 : }
4778 : :
4779 : : void
4780 : 32 : spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
4781 : : uint64_t timeout_io_us, uint64_t timeout_admin_us,
4782 : : spdk_nvme_timeout_cb cb_fn, void *cb_arg)
4783 : : {
4784 : : struct spdk_nvme_ctrlr_process *active_proc;
4785 : :
4786 : 32 : nvme_ctrlr_lock(ctrlr);
4787 : :
4788 : 32 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4789 [ + - ]: 32 : if (active_proc) {
4790 [ # # # # : 32 : active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL;
# # ]
4791 [ # # # # : 32 : active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL;
# # ]
4792 [ # # # # ]: 32 : active_proc->timeout_cb_fn = cb_fn;
4793 [ # # # # ]: 32 : active_proc->timeout_cb_arg = cb_arg;
4794 : 0 : }
4795 : :
4796 [ # # # # ]: 32 : ctrlr->timeout_enabled = true;
4797 : :
4798 : 32 : nvme_ctrlr_unlock(ctrlr);
4799 : 32 : }
4800 : :
4801 : : bool
4802 : 365 : spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
4803 : : {
4804 : : /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
4805 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
4806 [ - + # # : 365 : return ctrlr->log_page_supported[log_page];
# # # # #
# ]
4807 : : }
4808 : :
4809 : : bool
4810 : 12 : spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
4811 : : {
4812 : : /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
4813 : : SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
4814 [ - + # # : 12 : return ctrlr->feature_supported[feature_code];
# # # # #
# ]
4815 : : }
4816 : :
4817 : : int
4818 : 3 : spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4819 : : struct spdk_nvme_ctrlr_list *payload)
4820 : : {
4821 : : struct nvme_completion_poll_status *status;
4822 : : struct spdk_nvme_ns *ns;
4823 : : int res;
4824 : :
4825 [ - + ]: 3 : if (nsid == 0) {
4826 : 0 : return -EINVAL;
4827 : : }
4828 : :
4829 : 3 : status = calloc(1, sizeof(*status));
4830 [ - + ]: 3 : if (!status) {
4831 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
4832 : 0 : return -ENOMEM;
4833 : : }
4834 : :
4835 : 3 : res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
4836 : 0 : nvme_completion_poll_cb, status);
4837 [ - + ]: 3 : if (res) {
4838 : 0 : free(status);
4839 : 0 : return res;
4840 : : }
4841 [ - + # # : 3 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
4842 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n");
# # # # #
# # # # #
# # # # #
# ]
4843 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4844 : 0 : free(status);
4845 : 0 : }
4846 : 0 : return -ENXIO;
4847 : : }
4848 : 3 : free(status);
4849 : :
4850 : 3 : res = nvme_ctrlr_identify_active_ns(ctrlr);
4851 [ - + ]: 3 : if (res) {
4852 : 0 : return res;
4853 : : }
4854 : :
4855 : 3 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
4856 [ - + ]: 3 : if (ns == NULL) {
4857 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n");
# # # # #
# # # # #
# # # # #
# ]
4858 : 0 : return -ENXIO;
4859 : : }
4860 : :
4861 : 3 : return nvme_ns_construct(ns, nsid, ctrlr);
4862 : 0 : }
4863 : :
4864 : : int
4865 : 3 : spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4866 : : struct spdk_nvme_ctrlr_list *payload)
4867 : : {
4868 : : struct nvme_completion_poll_status *status;
4869 : : int res;
4870 : :
4871 [ - + ]: 3 : if (nsid == 0) {
4872 : 0 : return -EINVAL;
4873 : : }
4874 : :
4875 : 3 : status = calloc(1, sizeof(*status));
4876 [ - + ]: 3 : if (!status) {
4877 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
4878 : 0 : return -ENOMEM;
4879 : : }
4880 : :
4881 : 3 : res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
4882 : 0 : nvme_completion_poll_cb, status);
4883 [ - + ]: 3 : if (res) {
4884 : 0 : free(status);
4885 : 0 : return res;
4886 : : }
4887 [ - + # # : 3 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
4888 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n");
# # # # #
# # # # #
# # # # #
# ]
4889 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4890 : 0 : free(status);
4891 : 0 : }
4892 : 0 : return -ENXIO;
4893 : : }
4894 : 3 : free(status);
4895 : :
4896 : 3 : return nvme_ctrlr_identify_active_ns(ctrlr);
4897 : 0 : }
4898 : :
4899 : : uint32_t
4900 : 3 : spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
4901 : : {
4902 : : struct nvme_completion_poll_status *status;
4903 : : int res;
4904 : : uint32_t nsid;
4905 : :
4906 : 3 : status = calloc(1, sizeof(*status));
4907 [ - + ]: 3 : if (!status) {
4908 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
4909 : 0 : return 0;
4910 : : }
4911 : :
4912 : 3 : res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
4913 [ - + ]: 3 : if (res) {
4914 : 0 : free(status);
4915 : 0 : return 0;
4916 : : }
4917 [ - + # # : 3 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
4918 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n");
# # # # #
# # # # #
# # # # #
# ]
4919 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4920 : 0 : free(status);
4921 : 0 : }
4922 : 0 : return 0;
4923 : : }
4924 : :
4925 [ # # # # : 3 : nsid = status->cpl.cdw0;
# # ]
4926 : 3 : free(status);
4927 : :
4928 [ - + # # ]: 3 : assert(nsid > 0);
4929 : :
4930 : : /* Return the namespace ID that was created */
4931 : 3 : return nsid;
4932 : 0 : }
4933 : :
4934 : : int
4935 : 3 : spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4936 : : {
4937 : : struct nvme_completion_poll_status *status;
4938 : : int res;
4939 : :
4940 [ - + ]: 3 : if (nsid == 0) {
4941 : 0 : return -EINVAL;
4942 : : }
4943 : :
4944 : 3 : status = calloc(1, sizeof(*status));
4945 [ - + ]: 3 : if (!status) {
4946 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
4947 : 0 : return -ENOMEM;
4948 : : }
4949 : :
4950 : 3 : res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
4951 [ - + ]: 3 : if (res) {
4952 : 0 : free(status);
4953 : 0 : return res;
4954 : : }
4955 [ - + # # : 3 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
4956 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n");
# # # # #
# # # # #
# # # # #
# ]
4957 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4958 : 0 : free(status);
4959 : 0 : }
4960 : 0 : return -ENXIO;
4961 : : }
4962 : 3 : free(status);
4963 : :
4964 : 3 : return nvme_ctrlr_identify_active_ns(ctrlr);
4965 : 0 : }
4966 : :
4967 : : int
4968 : 0 : spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4969 : : struct spdk_nvme_format *format)
4970 : : {
4971 : : struct nvme_completion_poll_status *status;
4972 : : int res;
4973 : :
4974 : 0 : status = calloc(1, sizeof(*status));
4975 [ # # ]: 0 : if (!status) {
4976 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
4977 : 0 : return -ENOMEM;
4978 : : }
4979 : :
4980 : 0 : res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
4981 : 0 : status);
4982 [ # # ]: 0 : if (res) {
4983 : 0 : free(status);
4984 : 0 : return res;
4985 : : }
4986 [ # # # # : 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
4987 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n");
# # # # #
# # # # #
# # # # #
# ]
4988 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
4989 : 0 : free(status);
4990 : 0 : }
4991 : 0 : return -ENXIO;
4992 : : }
4993 : 0 : free(status);
4994 : :
4995 : 0 : return spdk_nvme_ctrlr_reset(ctrlr);
4996 : 0 : }
4997 : :
4998 : : int
4999 : 24 : spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
5000 : : int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
5001 : : {
5002 : 24 : struct spdk_nvme_fw_commit fw_commit;
5003 : : struct nvme_completion_poll_status *status;
5004 : : int res;
5005 : : unsigned int size_remaining;
5006 : : unsigned int offset;
5007 : : unsigned int transfer;
5008 : : uint8_t *p;
5009 : :
5010 [ - + ]: 24 : if (!completion_status) {
5011 : 0 : return -EINVAL;
5012 : : }
5013 [ - + ]: 24 : memset(completion_status, 0, sizeof(struct spdk_nvme_status));
5014 [ + + # # ]: 24 : if (size % 4) {
5015 [ + - # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n");
# # # # #
# # # # #
# # # # #
# ]
5016 : 3 : return -1;
5017 : : }
5018 : :
5019 : : /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
5020 : : * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
5021 : : */
5022 [ - + - - ]: 21 : if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
5023 : 0 : (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
5024 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n");
# # # # #
# # # # #
# # # # #
# ]
5025 : 0 : return -1;
5026 : : }
5027 : :
5028 : 21 : status = calloc(1, sizeof(*status));
5029 [ - + ]: 21 : if (!status) {
5030 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
5031 : 0 : return -ENOMEM;
5032 : : }
5033 : :
5034 : : /* Firmware download */
5035 : 21 : size_remaining = size;
5036 : 21 : offset = 0;
5037 : 21 : p = payload;
5038 : :
5039 [ + + ]: 30 : while (size_remaining > 0) {
5040 [ # # # # : 21 : transfer = spdk_min(size_remaining, ctrlr->min_page_size);
# # # # #
# ]
5041 : :
5042 [ - + ]: 21 : memset(status, 0, sizeof(*status));
5043 : 21 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
5044 : : nvme_completion_poll_cb,
5045 : 0 : status);
5046 [ + + ]: 21 : if (res) {
5047 : 6 : free(status);
5048 : 6 : return res;
5049 : : }
5050 : :
5051 [ + + # # : 15 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
5052 [ + - # # : 6 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5053 [ + + + + : 6 : if (!status->timed_out) {
# # # # ]
5054 : 3 : free(status);
5055 : 0 : }
5056 : 6 : return -ENXIO;
5057 : : }
5058 [ # # ]: 9 : p += transfer;
5059 : 9 : offset += transfer;
5060 : 9 : size_remaining -= transfer;
5061 : : }
5062 : :
5063 : : /* Firmware commit */
5064 [ - + ]: 9 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5065 : 9 : fw_commit.fs = slot;
5066 : 9 : fw_commit.ca = commit_action;
5067 : :
5068 [ - + ]: 9 : memset(status, 0, sizeof(*status));
5069 : 9 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
5070 : 0 : status);
5071 [ + + ]: 9 : if (res) {
5072 : 3 : free(status);
5073 : 3 : return res;
5074 : : }
5075 : :
5076 [ # # # # : 6 : res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
# # ]
5077 : :
5078 [ # # # # : 6 : memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
# # # # #
# ]
5079 : :
5080 [ + + + - : 6 : if (!status->timed_out) {
# # # # ]
5081 : 6 : free(status);
5082 : 0 : }
5083 : :
5084 [ + + ]: 6 : if (res) {
5085 [ - + # # : 3 : if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
# # ]
5086 [ # # ]: 0 : completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
5087 [ - + # # : 3 : if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
# # ]
5088 [ # # ]: 0 : completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
5089 [ # # # # : 0 : NVME_CTRLR_NOTICELOG(ctrlr,
# # # # #
# # # # #
# # # # #
# ]
5090 : : "firmware activation requires conventional reset to be performed. !\n");
5091 : 0 : } else {
5092 [ + - # # : 3 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5093 : : }
5094 : 3 : return -ENXIO;
5095 : : }
5096 : 0 : }
5097 : :
5098 : 3 : return spdk_nvme_ctrlr_reset(ctrlr);
5099 : 0 : }
5100 : :
5101 : : int
5102 : 0 : spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
5103 : : {
5104 : : int rc, size;
5105 : : union spdk_nvme_cmbsz_register cmbsz;
5106 : :
5107 : 0 : cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
5108 : :
5109 [ # # # # ]: 0 : if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
5110 : 0 : return -ENOTSUP;
5111 : : }
5112 : :
5113 [ # # # # : 0 : size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
# # # # ]
5114 : :
5115 : 0 : nvme_ctrlr_lock(ctrlr);
5116 : 0 : rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
5117 : 0 : nvme_ctrlr_unlock(ctrlr);
5118 : :
5119 [ # # ]: 0 : if (rc < 0) {
5120 : 0 : return rc;
5121 : : }
5122 : :
5123 : 0 : return size;
5124 : 0 : }
5125 : :
5126 : : void *
5127 : 19 : spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5128 : : {
5129 : : void *buf;
5130 : :
5131 : 19 : nvme_ctrlr_lock(ctrlr);
5132 : 19 : buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
5133 : 19 : nvme_ctrlr_unlock(ctrlr);
5134 : :
5135 : 19 : return buf;
5136 : : }
5137 : :
5138 : : void
5139 : 2 : spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
5140 : : {
5141 : 2 : nvme_ctrlr_lock(ctrlr);
5142 : 2 : nvme_transport_ctrlr_unmap_cmb(ctrlr);
5143 : 2 : nvme_ctrlr_unlock(ctrlr);
5144 : 2 : }
5145 : :
5146 : : int
5147 : 44 : spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5148 : : {
5149 : : int rc;
5150 : :
5151 : 44 : nvme_ctrlr_lock(ctrlr);
5152 : 44 : rc = nvme_transport_ctrlr_enable_pmr(ctrlr);
5153 : 44 : nvme_ctrlr_unlock(ctrlr);
5154 : :
5155 : 44 : return rc;
5156 : : }
5157 : :
5158 : : int
5159 : 44 : spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5160 : : {
5161 : : int rc;
5162 : :
5163 : 44 : nvme_ctrlr_lock(ctrlr);
5164 : 44 : rc = nvme_transport_ctrlr_disable_pmr(ctrlr);
5165 : 44 : nvme_ctrlr_unlock(ctrlr);
5166 : :
5167 : 44 : return rc;
5168 : : }
5169 : :
5170 : : void *
5171 : 44 : spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5172 : : {
5173 : : void *buf;
5174 : :
5175 : 44 : nvme_ctrlr_lock(ctrlr);
5176 : 44 : buf = nvme_transport_ctrlr_map_pmr(ctrlr, size);
5177 : 44 : nvme_ctrlr_unlock(ctrlr);
5178 : :
5179 : 44 : return buf;
5180 : : }
5181 : :
5182 : : int
5183 : 44 : spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
5184 : : {
5185 : : int rc;
5186 : :
5187 : 44 : nvme_ctrlr_lock(ctrlr);
5188 : 44 : rc = nvme_transport_ctrlr_unmap_pmr(ctrlr);
5189 : 44 : nvme_ctrlr_unlock(ctrlr);
5190 : :
5191 : 44 : return rc;
5192 : : }
5193 : :
5194 : : int
5195 : 0 : spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload,
5196 : : uint32_t bprsz, uint32_t bprof, uint32_t bpid)
5197 : : {
5198 : 0 : union spdk_nvme_bprsel_register bprsel;
5199 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5200 : 0 : uint64_t bpmbl, bpmb_size;
5201 : :
5202 [ # # # # : 0 : if (ctrlr->cap.bits.bps == 0) {
# # # # ]
5203 : 0 : return -ENOTSUP;
5204 : : }
5205 : :
5206 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5207 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
# # # # #
# # # # #
# # # # #
# ]
5208 : 0 : return -EIO;
5209 : : }
5210 : :
5211 [ # # ]: 0 : if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) {
5212 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n");
# # # # #
# # # # #
# # # # #
# ]
5213 : 0 : return -EALREADY;
5214 : : }
5215 : :
5216 : 0 : nvme_ctrlr_lock(ctrlr);
5217 : :
5218 : 0 : bpmb_size = bprsz * 4096;
5219 : 0 : bpmbl = spdk_vtophys(payload, &bpmb_size);
5220 [ # # ]: 0 : if (bpmbl == SPDK_VTOPHYS_ERROR) {
5221 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n");
# # # # #
# # # # #
# # # # #
# ]
5222 : 0 : nvme_ctrlr_unlock(ctrlr);
5223 : 0 : return -EFAULT;
5224 : : }
5225 : :
5226 [ # # ]: 0 : if (bpmb_size != bprsz * 4096) {
5227 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n");
# # # # #
# # # # #
# # # # #
# ]
5228 : 0 : nvme_ctrlr_unlock(ctrlr);
5229 : 0 : return -EFAULT;
5230 : : }
5231 : :
5232 [ # # ]: 0 : if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) {
5233 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n");
# # # # #
# # # # #
# # # # #
# ]
5234 : 0 : nvme_ctrlr_unlock(ctrlr);
5235 : 0 : return -EIO;
5236 : : }
5237 : :
5238 : 0 : bprsel.bits.bpid = bpid;
5239 : 0 : bprsel.bits.bprof = bprof;
5240 : 0 : bprsel.bits.bprsz = bprsz;
5241 : :
5242 [ # # ]: 0 : if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) {
5243 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n");
# # # # #
# # # # #
# # # # #
# ]
5244 : 0 : nvme_ctrlr_unlock(ctrlr);
5245 : 0 : return -EIO;
5246 : : }
5247 : :
5248 : 0 : nvme_ctrlr_unlock(ctrlr);
5249 : 0 : return 0;
5250 : 0 : }
5251 : :
5252 : : int
5253 : 0 : spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr)
5254 : : {
5255 : 0 : int rc = 0;
5256 : 0 : union spdk_nvme_bpinfo_register bpinfo;
5257 : :
5258 [ # # ]: 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5259 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
# # # # #
# # # # #
# # # # #
# ]
5260 : 0 : return -EIO;
5261 : : }
5262 : :
5263 [ # # # # : 0 : switch (bpinfo.bits.brs) {
# ]
5264 : 0 : case SPDK_NVME_BRS_NO_READ:
5265 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n");
# # # # #
# # # # #
# # # # #
# ]
5266 : 0 : rc = -EINVAL;
5267 : 0 : break;
5268 : 0 : case SPDK_NVME_BRS_READ_IN_PROGRESS:
5269 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
5270 : 0 : rc = -EAGAIN;
5271 : 0 : break;
5272 : 0 : case SPDK_NVME_BRS_READ_ERROR:
5273 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n");
# # # # #
# # # # #
# # # # #
# ]
5274 : 0 : rc = -EIO;
5275 : 0 : break;
5276 : 0 : case SPDK_NVME_BRS_READ_SUCCESS:
5277 [ # # # # : 0 : NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
5278 : 0 : break;
5279 : 0 : default:
5280 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n");
# # # # #
# # # # #
# # # # #
# ]
5281 : 0 : rc = -EINVAL;
5282 : 0 : }
5283 : :
5284 : 0 : return rc;
5285 : 0 : }
5286 : :
5287 : : static void
5288 : 0 : nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl)
5289 : : {
5290 : : int res;
5291 : 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
5292 : 0 : struct spdk_nvme_fw_commit fw_commit;
5293 : 0 : struct spdk_nvme_cpl err_cpl =
5294 : : {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }};
5295 : :
5296 [ # # # # : 0 : if (spdk_nvme_cpl_is_error(cpl)) {
# # # # #
# # # # #
# # ]
5297 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n");
# # # # #
# # # # #
# # # # #
# ]
5298 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
# # # # #
# # # ]
5299 : 0 : return;
5300 : : }
5301 : :
5302 [ # # # # : 0 : if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) {
# # ]
5303 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset);
# # # # #
# # # # #
# # # # #
# # # # #
# # # # #
# ]
5304 [ # # # # : 0 : ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size;
# # # # #
# # # #
# ]
5305 [ # # # # : 0 : ctrlr->fw_offset += ctrlr->fw_transfer_size;
# # # # ]
5306 [ # # # # : 0 : ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size;
# # # # ]
5307 [ # # # # : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
# # # # #
# # # # #
# # # # #
# # # ]
5308 [ # # # # : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
# # # # ]
5309 [ # # # # ]: 0 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5310 [ # # ]: 0 : if (res) {
5311 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5312 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5313 : 0 : return;
5314 : : }
5315 : :
5316 [ # # # # : 0 : if (ctrlr->fw_transfer_size < ctrlr->min_page_size) {
# # # # #
# ]
5317 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED;
5318 : 0 : }
5319 [ # # # # : 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) {
# # ]
5320 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
5321 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5322 [ # # # # ]: 0 : fw_commit.bpid = ctrlr->bpid;
5323 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION;
5324 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5325 : 0 : nvme_write_boot_partition_cb, ctrlr);
5326 [ # # ]: 0 : if (res) {
5327 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5328 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
# # # # #
# # # # #
# # # # #
# ]
5329 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5330 : 0 : return;
5331 : : }
5332 : :
5333 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE;
5334 [ # # # # : 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) {
# # ]
5335 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
5336 [ # # ]: 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5337 [ # # # # ]: 0 : fw_commit.bpid = ctrlr->bpid;
5338 : 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION;
5339 : 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5340 : 0 : nvme_write_boot_partition_cb, ctrlr);
5341 [ # # ]: 0 : if (res) {
5342 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5343 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
# # # # #
# # # # #
# # # # #
# ]
5344 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5345 : 0 : return;
5346 : : }
5347 : :
5348 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE;
5349 [ # # # # : 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) {
# # ]
5350 [ # # # # : 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n");
# # # # #
# # # # #
# # # # #
# # # # #
# # ]
5351 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
# # # # #
# # # ]
5352 : 0 : } else {
5353 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n");
# # # # #
# # # # #
# # # # #
# ]
5354 [ # # # # : 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
# # # # #
# # # ]
5355 : 0 : return;
5356 : : }
5357 : 0 : }
5358 : :
5359 : : int
5360 : 0 : spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr,
5361 : : void *payload, uint32_t size, uint32_t bpid,
5362 : : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
5363 : : {
5364 : : int res;
5365 : :
5366 [ # # # # : 0 : if (ctrlr->cap.bits.bps == 0) {
# # # # ]
5367 : 0 : return -ENOTSUP;
5368 : : }
5369 : :
5370 [ # # # # ]: 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING;
5371 [ # # # # ]: 0 : ctrlr->bpid = bpid;
5372 [ # # # # ]: 0 : ctrlr->bp_write_cb_fn = cb_fn;
5373 [ # # # # ]: 0 : ctrlr->bp_write_cb_arg = cb_arg;
5374 [ # # # # ]: 0 : ctrlr->fw_offset = 0;
5375 [ # # # # ]: 0 : ctrlr->fw_size_remaining = size;
5376 [ # # # # ]: 0 : ctrlr->fw_payload = payload;
5377 [ # # # # : 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
# # # # #
# # # # #
# # # # #
# # # ]
5378 : :
5379 [ # # # # : 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
# # # # ]
5380 [ # # # # ]: 0 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5381 : :
5382 : 0 : return res;
5383 : 0 : }
5384 : :
5385 : : bool
5386 : 10018 : spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
5387 : : {
5388 [ + + # # ]: 10018 : assert(ctrlr);
5389 : :
5390 [ + + + - : 10018 : return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
+ - + - ]
5391 : : strlen(SPDK_NVMF_DISCOVERY_NQN));
5392 : : }
5393 : :
5394 : : bool
5395 : 4292 : spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr)
5396 : : {
5397 [ + + # # ]: 4292 : assert(ctrlr);
5398 : :
5399 [ + - + - : 4292 : return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype);
+ - ]
5400 : : }
5401 : :
5402 : : int
5403 : 64 : spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5404 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5405 : : {
5406 : : struct nvme_completion_poll_status *status;
5407 : : int res;
5408 : :
5409 : 64 : status = calloc(1, sizeof(*status));
5410 [ - + ]: 64 : if (!status) {
5411 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
5412 : 0 : return -ENOMEM;
5413 : : }
5414 : :
5415 : 64 : res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
5416 : 0 : nvme_completion_poll_cb, status);
5417 [ - + ]: 64 : if (res) {
5418 : 0 : free(status);
5419 : 0 : return res;
5420 : : }
5421 [ - + # # : 64 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
5422 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5423 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
5424 : 0 : free(status);
5425 : 0 : }
5426 : 0 : return -ENXIO;
5427 : : }
5428 : 64 : free(status);
5429 : :
5430 : 64 : return 0;
5431 : 0 : }
5432 : :
5433 : : int
5434 : 0 : spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5435 : : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5436 : : {
5437 : : struct nvme_completion_poll_status *status;
5438 : : int res;
5439 : :
5440 : 0 : status = calloc(1, sizeof(*status));
5441 [ # # ]: 0 : if (!status) {
5442 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
# # # # #
# # # # #
# # # # #
# ]
5443 : 0 : return -ENOMEM;
5444 : : }
5445 : :
5446 : 0 : res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
5447 : : nvme_completion_poll_cb,
5448 : 0 : status);
5449 [ # # ]: 0 : if (res) {
5450 : 0 : free(status);
5451 : 0 : return res;
5452 : : }
5453 [ # # # # : 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
# # # # ]
5454 [ # # # # : 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n");
# # # # #
# # # # #
# # # # #
# ]
5455 [ # # # # : 0 : if (!status->timed_out) {
# # # # ]
5456 : 0 : free(status);
5457 : 0 : }
5458 : 0 : return -ENXIO;
5459 : : }
5460 : :
5461 : 0 : free(status);
5462 : :
5463 : 0 : return 0;
5464 : 0 : }
5465 : :
5466 : : uint64_t
5467 : 8033 : spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
5468 : : {
5469 [ + - + - ]: 8033 : return ctrlr->flags;
5470 : : }
5471 : :
5472 : : const struct spdk_nvme_transport_id *
5473 : 2417 : spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
5474 : : {
5475 [ # # ]: 2417 : return &ctrlr->trid;
5476 : : }
5477 : :
5478 : : int32_t
5479 : 5995 : spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
5480 : : {
5481 : : uint32_t qid;
5482 : :
5483 [ + + + - : 5995 : assert(ctrlr->free_io_qids);
+ - # # ]
5484 : 5995 : nvme_ctrlr_lock(ctrlr);
5485 [ + - + - ]: 5995 : qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
5486 [ + + + - : 5995 : if (qid > ctrlr->opts.num_io_queues) {
+ - - + ]
5487 [ + + # # : 8 : NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n");
# # # # #
# # # # #
# # # # #
# ]
5488 : 8 : nvme_ctrlr_unlock(ctrlr);
5489 : 8 : return -1;
5490 : : }
5491 : :
5492 [ + - + - ]: 5987 : spdk_bit_array_clear(ctrlr->free_io_qids, qid);
5493 : 5987 : nvme_ctrlr_unlock(ctrlr);
5494 : 5987 : return qid;
5495 : 817 : }
5496 : :
5497 : : void
5498 : 376554 : spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
5499 : : {
5500 [ + + + - : 376554 : assert(qid <= ctrlr->opts.num_io_queues);
+ - + - #
# ]
5501 : :
5502 : 376554 : nvme_ctrlr_lock(ctrlr);
5503 : :
5504 [ + + + - : 376554 : if (spdk_likely(ctrlr->free_io_qids)) {
- + ]
5505 [ + - + - ]: 376518 : spdk_bit_array_set(ctrlr->free_io_qids, qid);
5506 : 104578 : }
5507 : :
5508 : 376554 : nvme_ctrlr_unlock(ctrlr);
5509 : 376554 : }
5510 : :
5511 : : int
5512 : 10665 : spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
5513 : : struct spdk_memory_domain **domains, int array_size)
5514 : : {
5515 : 10665 : return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size);
5516 : : }
5517 : :
5518 : : int
5519 : 24 : spdk_nvme_ctrlr_authenticate(struct spdk_nvme_ctrlr *ctrlr,
5520 : : spdk_nvme_authenticate_cb cb_fn, void *cb_ctx)
5521 : : {
5522 [ # # # # ]: 24 : return spdk_nvme_qpair_authenticate(ctrlr->adminq, cb_fn, cb_ctx);
5523 : : }
|