Line data Source code
1 : /* SPDX-License-Identifier: BSD-3-Clause
2 : * Copyright (C) 2015 Intel Corporation. All rights reserved.
3 : * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.
4 : * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 : */
6 :
7 : #include "spdk/stdinc.h"
8 :
9 : #include "nvme_internal.h"
10 : #include "nvme_io_msg.h"
11 :
12 : #include "spdk/env.h"
13 : #include "spdk/string.h"
14 : #include "spdk/endian.h"
15 :
16 : struct nvme_active_ns_ctx;
17 :
18 : static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
19 : struct nvme_async_event_request *aer);
20 : static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
21 : static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
22 : static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
23 : static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
24 : static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr);
25 : static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
26 : uint64_t timeout_in_ms);
27 :
28 : static int
29 477891 : nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2)
30 : {
31 477891 : if (ns1->id < ns2->id) {
32 164867 : return -1;
33 313024 : } else if (ns1->id > ns2->id) {
34 276062 : return 1;
35 : } else {
36 36962 : return 0;
37 : }
38 : }
39 :
40 599405 : RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp);
41 :
42 : #define CTRLR_STRING(ctrlr) \
43 : ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \
44 : ctrlr->trid.subnqn : ctrlr->trid.traddr)
45 :
46 : #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \
47 : SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
48 :
49 : #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \
50 : SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
51 :
52 : #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \
53 : SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
54 :
55 : #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \
56 : SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
57 :
58 : #ifdef DEBUG
59 : #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \
60 : SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__);
61 : #else
62 : #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0)
63 : #endif
64 :
65 : #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \
66 : nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \
67 : offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg)
68 :
69 : #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \
70 : nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \
71 : offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg)
72 :
73 : #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \
74 : nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg)
75 :
76 : #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \
77 : nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg)
78 :
79 : #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \
80 : nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg)
81 :
82 : #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \
83 : nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg)
84 :
85 : #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \
86 : nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg)
87 :
88 : static int
89 0 : nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
90 : {
91 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
92 : &cc->raw);
93 : }
94 :
95 : static int
96 0 : nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
97 : {
98 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
99 : &csts->raw);
100 : }
101 :
102 : int
103 0 : nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
104 : {
105 0 : return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
106 : &cap->raw);
107 : }
108 :
109 : int
110 1 : nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
111 : {
112 1 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
113 : &vs->raw);
114 : }
115 :
116 : int
117 0 : nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
118 : {
119 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
120 : &cmbsz->raw);
121 : }
122 :
123 : int
124 0 : nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap)
125 : {
126 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw),
127 : &pmrcap->raw);
128 : }
129 :
130 : int
131 0 : nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo)
132 : {
133 0 : return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw),
134 : &bpinfo->raw);
135 : }
136 :
137 : int
138 0 : nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel)
139 : {
140 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw),
141 : bprsel->raw);
142 : }
143 :
144 : int
145 0 : nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value)
146 : {
147 0 : return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl),
148 : bpmbl_value);
149 : }
150 :
151 : static int
152 0 : nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
153 : {
154 0 : return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
155 : nssr_value);
156 : }
157 :
158 : bool
159 33 : nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
160 : {
161 35 : return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
162 2 : ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
163 : }
164 :
165 : /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
166 : * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
167 : */
168 : void
169 2 : spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
170 : {
171 2 : assert(opts);
172 :
173 2 : opts->opts_size = opts_size;
174 :
175 : #define FIELD_OK(field) \
176 : offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
177 :
178 : #define SET_FIELD(field, value) \
179 : if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
180 : opts->field = value; \
181 : } \
182 :
183 2 : SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
184 2 : SET_FIELD(use_cmb_sqs, false);
185 2 : SET_FIELD(no_shn_notification, false);
186 2 : SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
187 2 : SET_FIELD(arbitration_burst, 0);
188 2 : SET_FIELD(low_priority_weight, 0);
189 2 : SET_FIELD(medium_priority_weight, 0);
190 2 : SET_FIELD(high_priority_weight, 0);
191 2 : SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
192 2 : SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
193 2 : SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
194 :
195 2 : if (nvme_driver_init() == 0) {
196 2 : if (FIELD_OK(hostnqn)) {
197 1 : nvme_get_default_hostnqn(opts->hostnqn, sizeof(opts->hostnqn));
198 : }
199 :
200 2 : if (FIELD_OK(extended_host_id)) {
201 1 : memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
202 : sizeof(opts->extended_host_id));
203 : }
204 :
205 : }
206 :
207 2 : SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
208 :
209 2 : if (FIELD_OK(src_addr)) {
210 1 : memset(opts->src_addr, 0, sizeof(opts->src_addr));
211 : }
212 :
213 2 : if (FIELD_OK(src_svcid)) {
214 1 : memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
215 : }
216 :
217 2 : if (FIELD_OK(host_id)) {
218 1 : memset(opts->host_id, 0, sizeof(opts->host_id));
219 : }
220 :
221 2 : SET_FIELD(command_set, CHAR_BIT);
222 2 : SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
223 2 : SET_FIELD(header_digest, false);
224 2 : SET_FIELD(data_digest, false);
225 2 : SET_FIELD(disable_error_logging, false);
226 2 : SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
227 2 : SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
228 2 : SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
229 2 : SET_FIELD(disable_read_ana_log_page, false);
230 2 : SET_FIELD(disable_read_changed_ns_list_log_page, false);
231 2 : SET_FIELD(tls_psk, NULL);
232 2 : SET_FIELD(dhchap_key, NULL);
233 2 : SET_FIELD(dhchap_ctrlr_key, NULL);
234 2 : SET_FIELD(dhchap_digests,
235 : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA256) |
236 : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA384) |
237 : SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA512));
238 2 : SET_FIELD(dhchap_dhgroups,
239 : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_NULL) |
240 : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_2048) |
241 : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_3072) |
242 : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_4096) |
243 : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_6144) |
244 : SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_8192));
245 :
246 2 : if (FIELD_OK(psk)) {
247 1 : memset(opts->psk, 0, sizeof(opts->psk));
248 : }
249 :
250 : #undef FIELD_OK
251 : #undef SET_FIELD
252 2 : }
253 :
254 : const struct spdk_nvme_ctrlr_opts *
255 0 : spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr)
256 : {
257 0 : return &ctrlr->opts;
258 : }
259 :
260 : /**
261 : * This function will be called when the process allocates the IO qpair.
262 : * Note: the ctrlr_lock must be held when calling this function.
263 : */
264 : static void
265 15 : nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
266 : {
267 : struct spdk_nvme_ctrlr_process *active_proc;
268 15 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
269 :
270 15 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
271 15 : if (active_proc) {
272 0 : TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
273 0 : qpair->active_proc = active_proc;
274 : }
275 15 : }
276 :
277 : /**
278 : * This function will be called when the process frees the IO qpair.
279 : * Note: the ctrlr_lock must be held when calling this function.
280 : */
281 : static void
282 15 : nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
283 : {
284 : struct spdk_nvme_ctrlr_process *active_proc;
285 15 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
286 : struct spdk_nvme_qpair *active_qpair, *tmp_qpair;
287 :
288 15 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
289 15 : if (!active_proc) {
290 15 : return;
291 : }
292 :
293 0 : TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
294 : per_process_tailq, tmp_qpair) {
295 0 : if (active_qpair == qpair) {
296 0 : TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
297 : active_qpair, per_process_tailq);
298 :
299 0 : break;
300 : }
301 : }
302 : }
303 :
304 : void
305 27 : spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
306 : struct spdk_nvme_io_qpair_opts *opts,
307 : size_t opts_size)
308 : {
309 27 : assert(ctrlr);
310 :
311 27 : assert(opts);
312 :
313 27 : memset(opts, 0, opts_size);
314 :
315 : #define FIELD_OK(field) \
316 : offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
317 :
318 27 : if (FIELD_OK(qprio)) {
319 27 : opts->qprio = SPDK_NVME_QPRIO_URGENT;
320 : }
321 :
322 27 : if (FIELD_OK(io_queue_size)) {
323 27 : opts->io_queue_size = ctrlr->opts.io_queue_size;
324 : }
325 :
326 27 : if (FIELD_OK(io_queue_requests)) {
327 26 : opts->io_queue_requests = ctrlr->opts.io_queue_requests;
328 : }
329 :
330 27 : if (FIELD_OK(delay_cmd_submit)) {
331 26 : opts->delay_cmd_submit = false;
332 : }
333 :
334 27 : if (FIELD_OK(sq.vaddr)) {
335 26 : opts->sq.vaddr = NULL;
336 : }
337 :
338 27 : if (FIELD_OK(sq.paddr)) {
339 26 : opts->sq.paddr = 0;
340 : }
341 :
342 27 : if (FIELD_OK(sq.buffer_size)) {
343 26 : opts->sq.buffer_size = 0;
344 : }
345 :
346 27 : if (FIELD_OK(cq.vaddr)) {
347 26 : opts->cq.vaddr = NULL;
348 : }
349 :
350 27 : if (FIELD_OK(cq.paddr)) {
351 26 : opts->cq.paddr = 0;
352 : }
353 :
354 27 : if (FIELD_OK(cq.buffer_size)) {
355 26 : opts->cq.buffer_size = 0;
356 : }
357 :
358 27 : if (FIELD_OK(create_only)) {
359 26 : opts->create_only = false;
360 : }
361 :
362 27 : if (FIELD_OK(async_mode)) {
363 26 : opts->async_mode = false;
364 : }
365 :
366 : #undef FIELD_OK
367 27 : }
368 :
369 : static struct spdk_nvme_qpair *
370 22 : nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
371 : const struct spdk_nvme_io_qpair_opts *opts)
372 : {
373 : int32_t qid;
374 : struct spdk_nvme_qpair *qpair;
375 : union spdk_nvme_cc_register cc;
376 :
377 22 : if (!ctrlr) {
378 0 : return NULL;
379 : }
380 :
381 22 : nvme_ctrlr_lock(ctrlr);
382 22 : cc.raw = ctrlr->process_init_cc.raw;
383 :
384 22 : if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
385 2 : nvme_ctrlr_unlock(ctrlr);
386 2 : return NULL;
387 : }
388 :
389 : /*
390 : * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
391 : * default round robin arbitration method.
392 : */
393 20 : if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
394 3 : NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n");
395 3 : nvme_ctrlr_unlock(ctrlr);
396 3 : return NULL;
397 : }
398 :
399 17 : qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
400 17 : if (qid < 0) {
401 2 : nvme_ctrlr_unlock(ctrlr);
402 2 : return NULL;
403 : }
404 :
405 15 : qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
406 15 : if (qpair == NULL) {
407 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n");
408 0 : spdk_nvme_ctrlr_free_qid(ctrlr, qid);
409 0 : nvme_ctrlr_unlock(ctrlr);
410 0 : return NULL;
411 : }
412 :
413 15 : TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
414 :
415 15 : nvme_ctrlr_proc_add_io_qpair(qpair);
416 :
417 15 : nvme_ctrlr_unlock(ctrlr);
418 :
419 15 : return qpair;
420 : }
421 :
422 : int
423 15 : spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
424 : {
425 : int rc;
426 :
427 15 : if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
428 0 : return -EISCONN;
429 : }
430 :
431 15 : nvme_ctrlr_lock(ctrlr);
432 15 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
433 15 : nvme_ctrlr_unlock(ctrlr);
434 :
435 15 : if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
436 0 : spdk_delay_us(100);
437 : }
438 :
439 15 : return rc;
440 : }
441 :
442 : void
443 0 : spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
444 : {
445 0 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
446 :
447 0 : nvme_ctrlr_lock(ctrlr);
448 0 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
449 0 : nvme_ctrlr_unlock(ctrlr);
450 0 : }
451 :
452 : struct spdk_nvme_qpair *
453 23 : spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
454 : const struct spdk_nvme_io_qpair_opts *user_opts,
455 : size_t opts_size)
456 : {
457 :
458 23 : struct spdk_nvme_qpair *qpair = NULL;
459 23 : struct spdk_nvme_io_qpair_opts opts;
460 : int rc;
461 :
462 23 : nvme_ctrlr_lock(ctrlr);
463 :
464 23 : if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) {
465 : /* When controller is resetting or initializing, free_io_qids is deleted or not created yet.
466 : * We can't create IO qpair in that case */
467 1 : goto unlock;
468 : }
469 :
470 : /*
471 : * Get the default options, then overwrite them with the user-provided options
472 : * up to opts_size.
473 : *
474 : * This allows for extensions of the opts structure without breaking
475 : * ABI compatibility.
476 : */
477 22 : spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
478 22 : if (user_opts) {
479 18 : memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
480 :
481 : /* If user passes buffers, make sure they're big enough for the requested queue size */
482 18 : if (opts.sq.vaddr) {
483 0 : if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
484 0 : NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n",
485 : opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
486 0 : goto unlock;
487 : }
488 : }
489 18 : if (opts.cq.vaddr) {
490 0 : if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
491 0 : NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n",
492 : opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
493 0 : goto unlock;
494 : }
495 : }
496 : }
497 :
498 22 : qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
499 :
500 22 : if (qpair == NULL || opts.create_only == true) {
501 7 : goto unlock;
502 : }
503 :
504 15 : rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
505 15 : if (rc != 0) {
506 1 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n");
507 1 : nvme_ctrlr_proc_remove_io_qpair(qpair);
508 1 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
509 1 : spdk_bit_array_set(ctrlr->free_io_qids, qpair->id);
510 1 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
511 1 : qpair = NULL;
512 1 : goto unlock;
513 : }
514 :
515 23 : unlock:
516 23 : nvme_ctrlr_unlock(ctrlr);
517 :
518 23 : return qpair;
519 : }
520 :
521 : int
522 8 : spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
523 : {
524 : struct spdk_nvme_ctrlr *ctrlr;
525 : enum nvme_qpair_state qpair_state;
526 : int rc;
527 :
528 8 : assert(qpair != NULL);
529 8 : assert(nvme_qpair_is_admin_queue(qpair) == false);
530 8 : assert(qpair->ctrlr != NULL);
531 :
532 8 : ctrlr = qpair->ctrlr;
533 8 : nvme_ctrlr_lock(ctrlr);
534 8 : qpair_state = nvme_qpair_get_state(qpair);
535 :
536 8 : if (ctrlr->is_removed) {
537 2 : rc = -ENODEV;
538 2 : goto out;
539 : }
540 :
541 6 : if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
542 2 : rc = -EAGAIN;
543 2 : goto out;
544 : }
545 :
546 4 : if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
547 2 : rc = -ENXIO;
548 2 : goto out;
549 : }
550 :
551 2 : if (qpair_state != NVME_QPAIR_DISCONNECTED) {
552 1 : rc = 0;
553 1 : goto out;
554 : }
555 :
556 1 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
557 1 : if (rc) {
558 0 : rc = -EAGAIN;
559 0 : goto out;
560 : }
561 :
562 1 : out:
563 8 : nvme_ctrlr_unlock(ctrlr);
564 8 : return rc;
565 : }
566 :
567 : spdk_nvme_qp_failure_reason
568 0 : spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
569 : {
570 0 : return ctrlr->adminq->transport_failure_reason;
571 : }
572 :
573 : /*
574 : * This internal function will attempt to take the controller
575 : * lock before calling disconnect on a controller qpair.
576 : * Functions already holding the controller lock should
577 : * call nvme_transport_ctrlr_disconnect_qpair directly.
578 : */
579 : void
580 0 : nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
581 : {
582 0 : struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
583 :
584 0 : assert(ctrlr != NULL);
585 0 : nvme_ctrlr_lock(ctrlr);
586 0 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
587 0 : nvme_ctrlr_unlock(ctrlr);
588 0 : }
589 :
590 : int
591 14 : spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
592 : {
593 : struct spdk_nvme_ctrlr *ctrlr;
594 :
595 14 : if (qpair == NULL) {
596 0 : return 0;
597 : }
598 :
599 14 : ctrlr = qpair->ctrlr;
600 :
601 14 : if (qpair->in_completion_context) {
602 : /*
603 : * There are many cases where it is convenient to delete an io qpair in the context
604 : * of that qpair's completion routine. To handle this properly, set a flag here
605 : * so that the completion routine will perform an actual delete after the context
606 : * unwinds.
607 : */
608 0 : qpair->delete_after_completion_context = 1;
609 0 : return 0;
610 : }
611 :
612 14 : qpair->destroy_in_progress = 1;
613 :
614 14 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
615 :
616 14 : if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) {
617 0 : spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
618 : }
619 :
620 : /* Do not retry. */
621 14 : nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
622 :
623 : /* In the multi-process case, a process may call this function on a foreign
624 : * I/O qpair (i.e. one that this process did not create) when that qpairs process
625 : * exits unexpectedly. In that case, we must not try to abort any reqs associated
626 : * with that qpair, since the callbacks will also be foreign to this process.
627 : */
628 14 : if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
629 14 : nvme_qpair_abort_all_queued_reqs(qpair);
630 : }
631 :
632 14 : nvme_ctrlr_lock(ctrlr);
633 :
634 14 : nvme_ctrlr_proc_remove_io_qpair(qpair);
635 :
636 14 : TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
637 14 : spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
638 :
639 14 : nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
640 14 : nvme_ctrlr_unlock(ctrlr);
641 14 : return 0;
642 : }
643 :
644 : static void
645 3 : nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
646 : struct spdk_nvme_intel_log_page_directory *log_page_directory)
647 : {
648 3 : if (log_page_directory == NULL) {
649 0 : return;
650 : }
651 :
652 3 : assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL);
653 :
654 3 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
655 :
656 3 : if (log_page_directory->read_latency_log_len ||
657 2 : (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
658 2 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
659 : }
660 3 : if (log_page_directory->write_latency_log_len ||
661 2 : (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
662 2 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
663 : }
664 3 : if (log_page_directory->temperature_statistics_log_len) {
665 2 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
666 : }
667 3 : if (log_page_directory->smart_log_len) {
668 1 : ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
669 : }
670 3 : if (log_page_directory->marketing_description_log_len) {
671 1 : ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
672 : }
673 : }
674 :
675 : struct intel_log_pages_ctx {
676 : struct spdk_nvme_intel_log_page_directory log_page_directory;
677 : struct spdk_nvme_ctrlr *ctrlr;
678 : };
679 :
680 : static void
681 1 : nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl)
682 : {
683 1 : struct intel_log_pages_ctx *ctx = arg;
684 1 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
685 :
686 1 : if (!spdk_nvme_cpl_is_error(cpl)) {
687 1 : nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory);
688 : }
689 :
690 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
691 1 : ctrlr->opts.admin_timeout_ms);
692 1 : free(ctx);
693 1 : }
694 :
695 : static int
696 1 : nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
697 : {
698 1 : int rc = 0;
699 : struct intel_log_pages_ctx *ctx;
700 :
701 1 : ctx = calloc(1, sizeof(*ctx));
702 1 : if (!ctx) {
703 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
704 0 : ctrlr->opts.admin_timeout_ms);
705 0 : return 0;
706 : }
707 :
708 1 : ctx->ctrlr = ctrlr;
709 :
710 1 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
711 1 : SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory,
712 : sizeof(struct spdk_nvme_intel_log_page_directory),
713 : 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx);
714 1 : if (rc != 0) {
715 0 : free(ctx);
716 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
717 0 : ctrlr->opts.admin_timeout_ms);
718 0 : return 0;
719 : }
720 :
721 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES,
722 1 : ctrlr->opts.admin_timeout_ms);
723 :
724 1 : return 0;
725 : }
726 :
727 : static int
728 4 : nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
729 : {
730 : uint32_t ana_log_page_size;
731 :
732 4 : ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
733 4 : sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count *
734 : sizeof(uint32_t);
735 :
736 : /* Number of active namespaces may have changed.
737 : * Check if ANA log page fits into existing buffer.
738 : */
739 4 : if (ana_log_page_size > ctrlr->ana_log_page_size) {
740 : void *new_buffer;
741 :
742 4 : if (ctrlr->ana_log_page) {
743 1 : new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size);
744 : } else {
745 3 : new_buffer = calloc(1, ana_log_page_size);
746 : }
747 :
748 4 : if (!new_buffer) {
749 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n",
750 : ana_log_page_size);
751 0 : return -ENXIO;
752 : }
753 :
754 4 : ctrlr->ana_log_page = new_buffer;
755 4 : if (ctrlr->copied_ana_desc) {
756 1 : new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size);
757 : } else {
758 3 : new_buffer = calloc(1, ana_log_page_size);
759 : }
760 :
761 4 : if (!new_buffer) {
762 0 : NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n",
763 : ana_log_page_size);
764 0 : return -ENOMEM;
765 : }
766 :
767 4 : ctrlr->copied_ana_desc = new_buffer;
768 4 : ctrlr->ana_log_page_size = ana_log_page_size;
769 : }
770 :
771 4 : return 0;
772 : }
773 :
774 : static int
775 4 : nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
776 : {
777 : struct nvme_completion_poll_status *status;
778 : int rc;
779 :
780 4 : rc = nvme_ctrlr_alloc_ana_log_page(ctrlr);
781 4 : if (rc != 0) {
782 0 : return rc;
783 : }
784 :
785 4 : status = calloc(1, sizeof(*status));
786 4 : if (status == NULL) {
787 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
788 0 : return -ENOMEM;
789 : }
790 :
791 4 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
792 4 : SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
793 : ctrlr->ana_log_page_size, 0,
794 : nvme_completion_poll_cb, status);
795 4 : if (rc != 0) {
796 0 : free(status);
797 0 : return rc;
798 : }
799 :
800 4 : if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
801 4 : ctrlr->opts.admin_timeout_ms * 1000)) {
802 0 : if (!status->timed_out) {
803 0 : free(status);
804 : }
805 0 : return -EIO;
806 : }
807 :
808 4 : free(status);
809 4 : return 0;
810 : }
811 :
812 : static int
813 5 : nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
814 : void *cb_arg)
815 : {
816 5 : struct spdk_nvme_ctrlr *ctrlr = cb_arg;
817 : struct spdk_nvme_ns *ns;
818 : uint32_t i, nsid;
819 :
820 14 : for (i = 0; i < desc->num_of_nsid; i++) {
821 9 : nsid = desc->nsid[i];
822 9 : if (nsid == 0 || nsid > ctrlr->cdata.nn) {
823 0 : continue;
824 : }
825 :
826 9 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
827 9 : assert(ns != NULL);
828 :
829 9 : ns->ana_group_id = desc->ana_group_id;
830 9 : ns->ana_state = desc->ana_state;
831 : }
832 :
833 5 : return 0;
834 : }
835 :
836 : int
837 4 : nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
838 : spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
839 : {
840 : struct spdk_nvme_ana_group_descriptor *copied_desc;
841 : uint8_t *orig_desc;
842 : uint32_t i, desc_size, copy_len;
843 4 : int rc = 0;
844 :
845 4 : if (ctrlr->ana_log_page == NULL) {
846 0 : return -EINVAL;
847 : }
848 :
849 4 : copied_desc = ctrlr->copied_ana_desc;
850 :
851 4 : orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page);
852 4 : copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page);
853 :
854 9 : for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
855 5 : memcpy(copied_desc, orig_desc, copy_len);
856 :
857 5 : rc = cb_fn(copied_desc, cb_arg);
858 5 : if (rc != 0) {
859 0 : break;
860 : }
861 :
862 5 : desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) +
863 5 : copied_desc->num_of_nsid * sizeof(uint32_t);
864 5 : orig_desc += desc_size;
865 5 : copy_len -= desc_size;
866 : }
867 :
868 4 : return rc;
869 : }
870 :
871 : static int
872 16 : nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
873 : {
874 16 : int rc = 0;
875 :
876 16 : memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
877 : /* Mandatory pages */
878 16 : ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
879 16 : ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
880 16 : ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
881 16 : if (ctrlr->cdata.lpa.celp) {
882 1 : ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
883 : }
884 :
885 16 : if (ctrlr->cdata.cmic.ana_reporting) {
886 2 : ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
887 2 : if (!ctrlr->opts.disable_read_ana_log_page) {
888 2 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
889 2 : if (rc == 0) {
890 2 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
891 : ctrlr);
892 : }
893 : }
894 : }
895 :
896 16 : if (ctrlr->cdata.ctratt.bits.fdps) {
897 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true;
898 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true;
899 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true;
900 0 : ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true;
901 : }
902 :
903 16 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL &&
904 1 : ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE &&
905 1 : !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
906 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES,
907 1 : ctrlr->opts.admin_timeout_ms);
908 :
909 : } else {
910 15 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
911 15 : ctrlr->opts.admin_timeout_ms);
912 :
913 : }
914 :
915 16 : return rc;
916 : }
917 :
918 : static void
919 1 : nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
920 : {
921 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
922 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
923 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
924 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
925 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
926 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
927 1 : ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
928 1 : }
929 :
930 : static void
931 18 : nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
932 : {
933 : uint32_t cdw11;
934 : struct nvme_completion_poll_status *status;
935 :
936 18 : if (ctrlr->opts.arbitration_burst == 0) {
937 16 : return;
938 : }
939 :
940 2 : if (ctrlr->opts.arbitration_burst > 7) {
941 1 : NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n");
942 1 : return;
943 : }
944 :
945 1 : status = calloc(1, sizeof(*status));
946 1 : if (!status) {
947 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
948 0 : return;
949 : }
950 :
951 1 : cdw11 = ctrlr->opts.arbitration_burst;
952 :
953 1 : if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
954 1 : cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
955 1 : cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
956 1 : cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
957 : }
958 :
959 1 : if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
960 : cdw11, 0, NULL, 0,
961 : nvme_completion_poll_cb, status) < 0) {
962 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n");
963 0 : free(status);
964 0 : return;
965 : }
966 :
967 1 : if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
968 1 : ctrlr->opts.admin_timeout_ms * 1000)) {
969 0 : NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n");
970 : }
971 :
972 1 : if (!status->timed_out) {
973 1 : free(status);
974 : }
975 : }
976 :
977 : static void
978 16 : nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
979 : {
980 16 : memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
981 : /* Mandatory features */
982 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
983 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
984 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
985 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
986 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
987 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
988 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
989 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
990 16 : ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
991 : /* Optional features */
992 16 : if (ctrlr->cdata.vwc.present) {
993 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
994 : }
995 16 : if (ctrlr->cdata.apsta.supported) {
996 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
997 : }
998 16 : if (ctrlr->cdata.hmpre) {
999 0 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
1000 : }
1001 16 : if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
1002 1 : nvme_ctrlr_set_intel_supported_features(ctrlr);
1003 : }
1004 :
1005 16 : nvme_ctrlr_set_arbitration_feature(ctrlr);
1006 16 : }
1007 :
1008 : static void
1009 1 : nvme_ctrlr_set_host_feature_done(void *arg, const struct spdk_nvme_cpl *cpl)
1010 : {
1011 1 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1012 :
1013 1 : spdk_free(ctrlr->tmp_ptr);
1014 1 : ctrlr->tmp_ptr = NULL;
1015 :
1016 1 : if (spdk_nvme_cpl_is_error(cpl)) {
1017 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set host behavior support feature failed: SC %x SCT %x\n",
1018 : cpl->status.sc, cpl->status.sct);
1019 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1020 0 : return;
1021 : }
1022 :
1023 1 : ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT] = true;
1024 :
1025 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
1026 1 : ctrlr->opts.admin_timeout_ms);
1027 : }
1028 :
1029 : /* We do not want to do add synchronous operation anymore.
1030 : * We set the Host Behavior Support feature asynchronousin in different states.
1031 : */
1032 : static int
1033 16 : nvme_ctrlr_set_host_feature(struct spdk_nvme_ctrlr *ctrlr)
1034 : {
1035 : struct spdk_nvme_host_behavior *host;
1036 : int rc;
1037 :
1038 16 : if (!ctrlr->cdata.ctratt.bits.elbas) {
1039 15 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
1040 15 : ctrlr->opts.admin_timeout_ms);
1041 15 : return 0;
1042 : }
1043 :
1044 1 : ctrlr->tmp_ptr = spdk_dma_zmalloc(sizeof(struct spdk_nvme_host_behavior), 4096, NULL);
1045 1 : if (!ctrlr->tmp_ptr) {
1046 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate host behavior support data\n");
1047 0 : rc = -ENOMEM;
1048 0 : goto error;
1049 : }
1050 :
1051 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE,
1052 1 : ctrlr->opts.admin_timeout_ms);
1053 :
1054 1 : host = ctrlr->tmp_ptr;
1055 :
1056 1 : host->lbafee = 1;
1057 :
1058 1 : rc = spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT,
1059 : 0, 0, host, sizeof(struct spdk_nvme_host_behavior),
1060 : nvme_ctrlr_set_host_feature_done, ctrlr);
1061 1 : if (rc != 0) {
1062 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set host behavior support feature failed: %d\n", rc);
1063 0 : goto error;
1064 : }
1065 :
1066 1 : return 0;
1067 :
1068 0 : error:
1069 0 : spdk_free(ctrlr->tmp_ptr);
1070 0 : ctrlr->tmp_ptr = NULL;
1071 :
1072 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1073 0 : return rc;
1074 : }
1075 :
1076 : bool
1077 0 : spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
1078 : {
1079 0 : return ctrlr->is_failed;
1080 : }
1081 :
1082 : void
1083 1 : nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
1084 : {
1085 : /*
1086 : * Set the flag here and leave the work failure of qpairs to
1087 : * spdk_nvme_qpair_process_completions().
1088 : */
1089 1 : if (hot_remove) {
1090 0 : ctrlr->is_removed = true;
1091 : }
1092 :
1093 1 : if (ctrlr->is_failed) {
1094 0 : NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n");
1095 0 : return;
1096 : }
1097 :
1098 1 : if (ctrlr->is_disconnecting) {
1099 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n");
1100 0 : return;
1101 : }
1102 :
1103 1 : ctrlr->is_failed = true;
1104 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1105 1 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1106 1 : NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n");
1107 : }
1108 :
1109 : /**
1110 : * This public API function will try to take the controller lock.
1111 : * Any private functions being called from a thread already holding
1112 : * the ctrlr lock should call nvme_ctrlr_fail directly.
1113 : */
1114 : void
1115 0 : spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
1116 : {
1117 0 : nvme_ctrlr_lock(ctrlr);
1118 0 : nvme_ctrlr_fail(ctrlr, false);
1119 0 : nvme_ctrlr_unlock(ctrlr);
1120 0 : }
1121 :
1122 : static void
1123 39 : nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1124 : {
1125 39 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1126 39 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1127 :
1128 39 : if (spdk_nvme_cpl_is_error(cpl)) {
1129 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1130 0 : ctx->shutdown_complete = true;
1131 0 : return;
1132 : }
1133 :
1134 39 : if (ctrlr->opts.no_shn_notification) {
1135 0 : ctx->shutdown_complete = true;
1136 0 : return;
1137 : }
1138 :
1139 : /*
1140 : * The NVMe specification defines RTD3E to be the time between
1141 : * setting SHN = 1 until the controller will set SHST = 10b.
1142 : * If the device doesn't report RTD3 entry latency, or if it
1143 : * reports RTD3 entry latency less than 10 seconds, pick
1144 : * 10 seconds as a reasonable amount of time to
1145 : * wait before proceeding.
1146 : */
1147 39 : NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
1148 39 : ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
1149 39 : ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
1150 39 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms);
1151 :
1152 39 : ctx->shutdown_start_tsc = spdk_get_ticks();
1153 39 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1154 : }
1155 :
1156 : static void
1157 39 : nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1158 : {
1159 39 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1160 39 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1161 : union spdk_nvme_cc_register cc;
1162 : int rc;
1163 :
1164 39 : if (spdk_nvme_cpl_is_error(cpl)) {
1165 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1166 0 : ctx->shutdown_complete = true;
1167 0 : return;
1168 : }
1169 :
1170 39 : assert(value <= UINT32_MAX);
1171 39 : cc.raw = (uint32_t)value;
1172 :
1173 39 : if (ctrlr->opts.no_shn_notification) {
1174 0 : NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n");
1175 0 : if (cc.bits.en == 0) {
1176 0 : ctx->shutdown_complete = true;
1177 0 : return;
1178 : }
1179 :
1180 0 : cc.bits.en = 0;
1181 : } else {
1182 39 : cc.bits.shn = SPDK_NVME_SHN_NORMAL;
1183 : }
1184 :
1185 39 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx);
1186 39 : if (rc != 0) {
1187 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n");
1188 0 : ctx->shutdown_complete = true;
1189 : }
1190 : }
1191 :
1192 : static void
1193 47 : nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
1194 : struct nvme_ctrlr_detach_ctx *ctx)
1195 : {
1196 : int rc;
1197 :
1198 47 : if (ctrlr->is_removed) {
1199 0 : ctx->shutdown_complete = true;
1200 0 : return;
1201 : }
1202 :
1203 47 : if (ctrlr->adminq == NULL ||
1204 40 : ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) {
1205 8 : NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n");
1206 8 : ctx->shutdown_complete = true;
1207 8 : return;
1208 : }
1209 :
1210 39 : ctx->state = NVME_CTRLR_DETACH_SET_CC;
1211 39 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx);
1212 39 : if (rc != 0) {
1213 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
1214 0 : ctx->shutdown_complete = true;
1215 : }
1216 : }
1217 :
1218 : static void
1219 39 : nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1220 : {
1221 39 : struct nvme_ctrlr_detach_ctx *ctx = _ctx;
1222 :
1223 39 : if (spdk_nvme_cpl_is_error(cpl)) {
1224 0 : NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n");
1225 0 : ctx->shutdown_complete = true;
1226 0 : return;
1227 : }
1228 :
1229 39 : assert(value <= UINT32_MAX);
1230 39 : ctx->csts.raw = (uint32_t)value;
1231 39 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE;
1232 : }
1233 :
1234 : static int
1235 78 : nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
1236 : struct nvme_ctrlr_detach_ctx *ctx)
1237 : {
1238 : union spdk_nvme_csts_register csts;
1239 : uint32_t ms_waited;
1240 :
1241 78 : switch (ctx->state) {
1242 0 : case NVME_CTRLR_DETACH_SET_CC:
1243 : case NVME_CTRLR_DETACH_GET_CSTS:
1244 : /* We're still waiting for the register operation to complete */
1245 0 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1246 0 : return -EAGAIN;
1247 :
1248 39 : case NVME_CTRLR_DETACH_CHECK_CSTS:
1249 39 : ctx->state = NVME_CTRLR_DETACH_GET_CSTS;
1250 39 : if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) {
1251 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
1252 0 : return -EIO;
1253 : }
1254 39 : return -EAGAIN;
1255 :
1256 39 : case NVME_CTRLR_DETACH_GET_CSTS_DONE:
1257 39 : ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS;
1258 39 : break;
1259 :
1260 0 : default:
1261 0 : assert(0 && "Should never happen");
1262 : return -EINVAL;
1263 : }
1264 :
1265 39 : ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
1266 39 : csts.raw = ctx->csts.raw;
1267 :
1268 39 : if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
1269 39 : NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited);
1270 39 : return 0;
1271 : }
1272 :
1273 0 : if (ms_waited < ctx->shutdown_timeout_ms) {
1274 0 : return -EAGAIN;
1275 : }
1276 :
1277 0 : NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n",
1278 : ctx->shutdown_timeout_ms);
1279 0 : if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
1280 0 : NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
1281 : }
1282 :
1283 0 : return 0;
1284 : }
1285 :
1286 : static inline uint64_t
1287 509 : nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr)
1288 : {
1289 509 : return ctrlr->cap.bits.to * 500;
1290 : }
1291 :
1292 : static void
1293 14 : nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
1294 : {
1295 14 : struct spdk_nvme_ctrlr *ctrlr = ctx;
1296 :
1297 14 : if (spdk_nvme_cpl_is_error(cpl)) {
1298 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n");
1299 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1300 0 : return;
1301 : }
1302 :
1303 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
1304 : nvme_ctrlr_get_ready_timeout(ctrlr));
1305 : }
1306 :
1307 : static int
1308 21 : nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
1309 : {
1310 : union spdk_nvme_cc_register cc;
1311 : int rc;
1312 :
1313 21 : rc = nvme_transport_ctrlr_enable(ctrlr);
1314 21 : if (rc != 0) {
1315 0 : NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n");
1316 0 : return rc;
1317 : }
1318 :
1319 21 : cc.raw = ctrlr->process_init_cc.raw;
1320 21 : if (cc.bits.en != 0) {
1321 0 : NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n");
1322 0 : return -EINVAL;
1323 : }
1324 :
1325 21 : cc.bits.en = 1;
1326 21 : cc.bits.css = 0;
1327 21 : cc.bits.shn = 0;
1328 21 : cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1329 21 : cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1330 :
1331 : /* Page size is 2 ^ (12 + mps). */
1332 21 : cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1333 :
1334 : /*
1335 : * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1336 : * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1337 : * Try to support such a controller regardless.
1338 : */
1339 21 : if (ctrlr->cap.bits.css == 0) {
1340 21 : NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n");
1341 21 : ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
1342 : }
1343 :
1344 : /*
1345 : * If the user did not explicitly request a command set, or supplied a value larger than
1346 : * what can be saved in CC.CSS, use the most reasonable default.
1347 : */
1348 21 : if (ctrlr->opts.command_set >= CHAR_BIT) {
1349 0 : if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
1350 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
1351 0 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
1352 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1353 0 : } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
1354 : /* Technically we should respond with CC_CSS_NOIO in
1355 : * this case, but we use NVM instead to work around
1356 : * buggy targets and to match Linux driver behavior.
1357 : */
1358 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1359 : } else {
1360 : /* Invalid supported bits detected, falling back to NVM. */
1361 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1362 : }
1363 : }
1364 :
1365 : /* Verify that the selected command set is supported by the controller. */
1366 21 : if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
1367 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n",
1368 : ctrlr->opts.command_set, ctrlr->cap.bits.css);
1369 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n");
1370 0 : ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1371 : }
1372 :
1373 21 : cc.bits.css = ctrlr->opts.command_set;
1374 :
1375 21 : switch (ctrlr->opts.arb_mechanism) {
1376 10 : case SPDK_NVME_CC_AMS_RR:
1377 10 : break;
1378 4 : case SPDK_NVME_CC_AMS_WRR:
1379 4 : if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
1380 2 : break;
1381 : }
1382 2 : return -EINVAL;
1383 4 : case SPDK_NVME_CC_AMS_VS:
1384 4 : if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
1385 2 : break;
1386 : }
1387 2 : return -EINVAL;
1388 3 : default:
1389 3 : return -EINVAL;
1390 : }
1391 :
1392 14 : cc.bits.ams = ctrlr->opts.arb_mechanism;
1393 14 : ctrlr->process_init_cc.raw = cc.raw;
1394 :
1395 14 : if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) {
1396 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
1397 0 : return -EIO;
1398 : }
1399 :
1400 14 : return 0;
1401 : }
1402 :
1403 : static const char *
1404 1 : nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1405 : {
1406 1 : switch (state) {
1407 0 : case NVME_CTRLR_STATE_INIT_DELAY:
1408 0 : return "delay init";
1409 0 : case NVME_CTRLR_STATE_CONNECT_ADMINQ:
1410 0 : return "connect adminq";
1411 0 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
1412 0 : return "wait for connect adminq";
1413 0 : case NVME_CTRLR_STATE_READ_VS:
1414 0 : return "read vs";
1415 0 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
1416 0 : return "read vs wait for vs";
1417 0 : case NVME_CTRLR_STATE_READ_CAP:
1418 0 : return "read cap";
1419 0 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
1420 0 : return "read cap wait for cap";
1421 0 : case NVME_CTRLR_STATE_CHECK_EN:
1422 0 : return "check en";
1423 0 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
1424 0 : return "check en wait for cc";
1425 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1426 0 : return "disable and wait for CSTS.RDY = 1";
1427 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1428 0 : return "disable and wait for CSTS.RDY = 1 reg";
1429 0 : case NVME_CTRLR_STATE_SET_EN_0:
1430 0 : return "set CC.EN = 0";
1431 0 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
1432 0 : return "set CC.EN = 0 wait for cc";
1433 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1434 0 : return "disable and wait for CSTS.RDY = 0";
1435 0 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
1436 0 : return "disable and wait for CSTS.RDY = 0 reg";
1437 0 : case NVME_CTRLR_STATE_DISABLED:
1438 0 : return "controller is disabled";
1439 0 : case NVME_CTRLR_STATE_ENABLE:
1440 0 : return "enable controller by writing CC.EN = 1";
1441 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
1442 0 : return "enable controller by writing CC.EN = 1 reg";
1443 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1444 0 : return "wait for CSTS.RDY = 1";
1445 0 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
1446 0 : return "wait for CSTS.RDY = 1 reg";
1447 0 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1448 0 : return "reset admin queue";
1449 0 : case NVME_CTRLR_STATE_IDENTIFY:
1450 0 : return "identify controller";
1451 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1452 0 : return "wait for identify controller";
1453 0 : case NVME_CTRLR_STATE_CONFIGURE_AER:
1454 0 : return "configure AER";
1455 0 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1456 0 : return "wait for configure aer";
1457 0 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1458 0 : return "set keep alive timeout";
1459 0 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1460 0 : return "wait for set keep alive timeout";
1461 0 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1462 0 : return "identify controller iocs specific";
1463 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1464 0 : return "wait for identify controller iocs specific";
1465 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1466 0 : return "get zns cmd and effects log page";
1467 0 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1468 0 : return "wait for get zns cmd and effects log page";
1469 0 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1470 0 : return "set number of queues";
1471 0 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1472 0 : return "wait for set number of queues";
1473 0 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1474 0 : return "identify active ns";
1475 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1476 0 : return "wait for identify active ns";
1477 0 : case NVME_CTRLR_STATE_IDENTIFY_NS:
1478 0 : return "identify ns";
1479 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1480 0 : return "wait for identify ns";
1481 0 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1482 0 : return "identify namespace id descriptors";
1483 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1484 0 : return "wait for identify namespace id descriptors";
1485 0 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1486 0 : return "identify ns iocs specific";
1487 0 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1488 0 : return "wait for identify ns iocs specific";
1489 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1490 0 : return "set supported log pages";
1491 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
1492 0 : return "set supported INTEL log pages";
1493 0 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
1494 0 : return "wait for supported INTEL log pages";
1495 0 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1496 0 : return "set supported features";
1497 0 : case NVME_CTRLR_STATE_SET_HOST_FEATURE:
1498 0 : return "set host behavior support feature";
1499 0 : case NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE:
1500 0 : return "wait for set host behavior support feature";
1501 0 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1502 0 : return "set doorbell buffer config";
1503 0 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1504 0 : return "wait for doorbell buffer config";
1505 0 : case NVME_CTRLR_STATE_SET_HOST_ID:
1506 0 : return "set host ID";
1507 0 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1508 0 : return "wait for set host ID";
1509 0 : case NVME_CTRLR_STATE_TRANSPORT_READY:
1510 0 : return "transport ready";
1511 0 : case NVME_CTRLR_STATE_READY:
1512 0 : return "ready";
1513 1 : case NVME_CTRLR_STATE_ERROR:
1514 1 : return "error";
1515 0 : case NVME_CTRLR_STATE_DISCONNECTED:
1516 0 : return "disconnected";
1517 : }
1518 0 : return "unknown";
1519 : };
1520 :
1521 : static void
1522 732 : _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1523 : uint64_t timeout_in_ms, bool quiet)
1524 : {
1525 : uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1526 :
1527 732 : ctrlr->state = state;
1528 732 : if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) {
1529 33 : if (!quiet) {
1530 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n",
1531 : nvme_ctrlr_state_string(ctrlr->state));
1532 : }
1533 33 : return;
1534 : }
1535 :
1536 699 : if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1537 697 : goto inf;
1538 : }
1539 :
1540 2 : ticks_per_ms = spdk_get_ticks_hz() / 1000;
1541 2 : if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1542 0 : NVME_CTRLR_ERRLOG(ctrlr,
1543 : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1544 0 : goto inf;
1545 : }
1546 :
1547 2 : now_ticks = spdk_get_ticks();
1548 2 : timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1549 2 : if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1550 1 : NVME_CTRLR_ERRLOG(ctrlr,
1551 : "Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1552 1 : goto inf;
1553 : }
1554 :
1555 1 : ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1556 1 : if (!quiet) {
1557 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n",
1558 : nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1559 : }
1560 1 : return;
1561 698 : inf:
1562 698 : if (!quiet) {
1563 698 : NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n",
1564 : nvme_ctrlr_state_string(ctrlr->state));
1565 : }
1566 698 : ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1567 : }
1568 :
1569 : static void
1570 699 : nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1571 : uint64_t timeout_in_ms)
1572 : {
1573 699 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false);
1574 699 : }
1575 :
1576 : static void
1577 33 : nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1578 : uint64_t timeout_in_ms)
1579 : {
1580 33 : _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true);
1581 33 : }
1582 :
1583 : static void
1584 48 : nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1585 : {
1586 48 : spdk_free(ctrlr->cdata_zns);
1587 48 : ctrlr->cdata_zns = NULL;
1588 48 : }
1589 :
1590 : static void
1591 48 : nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1592 : {
1593 48 : nvme_ctrlr_free_zns_specific_data(ctrlr);
1594 48 : }
1595 :
1596 : static void
1597 49 : nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1598 : {
1599 49 : if (ctrlr->shadow_doorbell) {
1600 1 : spdk_free(ctrlr->shadow_doorbell);
1601 1 : ctrlr->shadow_doorbell = NULL;
1602 : }
1603 :
1604 49 : if (ctrlr->eventidx) {
1605 1 : spdk_free(ctrlr->eventidx);
1606 1 : ctrlr->eventidx = NULL;
1607 : }
1608 49 : }
1609 :
1610 : static void
1611 1 : nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1612 : {
1613 1 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1614 :
1615 1 : if (spdk_nvme_cpl_is_error(cpl)) {
1616 0 : NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n");
1617 : } else {
1618 1 : NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n");
1619 : }
1620 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1621 1 : ctrlr->opts.admin_timeout_ms);
1622 1 : }
1623 :
1624 : static int
1625 15 : nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1626 : {
1627 15 : int rc = 0;
1628 15 : uint64_t prp1, prp2, len;
1629 :
1630 15 : if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
1631 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1632 14 : ctrlr->opts.admin_timeout_ms);
1633 14 : return 0;
1634 : }
1635 :
1636 1 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
1637 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
1638 0 : ctrlr->opts.admin_timeout_ms);
1639 0 : return 0;
1640 : }
1641 :
1642 : /* only 1 page size for doorbell buffer */
1643 1 : ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1644 : NULL, SPDK_ENV_LCORE_ID_ANY,
1645 : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1646 1 : if (ctrlr->shadow_doorbell == NULL) {
1647 0 : rc = -ENOMEM;
1648 0 : goto error;
1649 : }
1650 :
1651 1 : len = ctrlr->page_size;
1652 1 : prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1653 1 : if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1654 0 : rc = -EFAULT;
1655 0 : goto error;
1656 : }
1657 :
1658 1 : ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1659 : NULL, SPDK_ENV_LCORE_ID_ANY,
1660 : SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1661 1 : if (ctrlr->eventidx == NULL) {
1662 0 : rc = -ENOMEM;
1663 0 : goto error;
1664 : }
1665 :
1666 1 : len = ctrlr->page_size;
1667 1 : prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1668 1 : if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1669 0 : rc = -EFAULT;
1670 0 : goto error;
1671 : }
1672 :
1673 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1674 1 : ctrlr->opts.admin_timeout_ms);
1675 :
1676 1 : rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1677 : nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1678 1 : if (rc != 0) {
1679 0 : goto error;
1680 : }
1681 :
1682 1 : return 0;
1683 :
1684 0 : error:
1685 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1686 0 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1687 0 : return rc;
1688 : }
1689 :
1690 : void
1691 48 : nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1692 : {
1693 : struct nvme_request *req, *tmp;
1694 48 : struct spdk_nvme_cpl cpl = {};
1695 :
1696 48 : cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1697 48 : cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1698 :
1699 48 : STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
1700 0 : STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
1701 0 : ctrlr->outstanding_aborts++;
1702 :
1703 0 : nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
1704 : }
1705 48 : }
1706 :
1707 : static int
1708 2 : nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1709 : {
1710 2 : if (ctrlr->is_resetting || ctrlr->is_removed) {
1711 : /*
1712 : * Controller is already resetting or has been removed. Return
1713 : * immediately since there is no need to kick off another
1714 : * reset in these cases.
1715 : */
1716 1 : return ctrlr->is_resetting ? -EBUSY : -ENXIO;
1717 : }
1718 :
1719 1 : ctrlr->is_resetting = true;
1720 1 : ctrlr->is_failed = false;
1721 1 : ctrlr->is_disconnecting = true;
1722 1 : ctrlr->prepare_for_reset = true;
1723 :
1724 1 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n");
1725 :
1726 : /* Disable keep-alive, it'll be re-enabled as part of the init process */
1727 1 : ctrlr->keep_alive_interval_ticks = 0;
1728 :
1729 : /* Abort all of the queued abort requests */
1730 1 : nvme_ctrlr_abort_queued_aborts(ctrlr);
1731 :
1732 1 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1733 :
1734 1 : ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1735 1 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1736 :
1737 1 : return 0;
1738 : }
1739 :
1740 : static void
1741 1 : nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr)
1742 : {
1743 1 : assert(ctrlr->is_failed == false);
1744 1 : ctrlr->is_disconnecting = false;
1745 :
1746 : /* Doorbell buffer config is invalid during reset */
1747 1 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
1748 :
1749 : /* I/O Command Set Specific Identify Controller data is invalidated during reset */
1750 1 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
1751 :
1752 1 : spdk_bit_array_free(&ctrlr->free_io_qids);
1753 :
1754 : /* Set the state back to DISCONNECTED to cause a full hardware reset. */
1755 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE);
1756 1 : }
1757 :
1758 : int
1759 0 : spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr)
1760 : {
1761 : int rc;
1762 :
1763 0 : nvme_ctrlr_lock(ctrlr);
1764 0 : rc = nvme_ctrlr_disconnect(ctrlr);
1765 0 : nvme_ctrlr_unlock(ctrlr);
1766 :
1767 0 : return rc;
1768 : }
1769 :
1770 : void
1771 1 : spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr)
1772 : {
1773 1 : nvme_ctrlr_lock(ctrlr);
1774 :
1775 1 : ctrlr->prepare_for_reset = false;
1776 :
1777 : /* Set the state back to INIT to cause a full hardware reset. */
1778 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1779 :
1780 : /* Return without releasing ctrlr_lock. ctrlr_lock will be released when
1781 : * spdk_nvme_ctrlr_reset_poll_async() returns 0.
1782 : */
1783 1 : }
1784 :
1785 : int
1786 0 : nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
1787 : {
1788 : bool async;
1789 : int rc;
1790 :
1791 0 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc ||
1792 0 : spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) {
1793 0 : assert(false);
1794 : return -EINVAL;
1795 : }
1796 :
1797 : /* Force a synchronous connect. */
1798 0 : async = qpair->async;
1799 0 : qpair->async = false;
1800 0 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1801 0 : qpair->async = async;
1802 :
1803 0 : if (rc != 0) {
1804 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1805 : }
1806 :
1807 0 : return rc;
1808 : }
1809 :
1810 : /**
1811 : * This function will be called when the controller is being reinitialized.
1812 : * Note: the ctrlr_lock must be held when calling this function.
1813 : */
1814 : int
1815 25 : spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr)
1816 : {
1817 : struct spdk_nvme_ns *ns, *tmp_ns;
1818 : struct spdk_nvme_qpair *qpair;
1819 25 : int rc = 0, rc_tmp = 0;
1820 :
1821 25 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1822 0 : NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n");
1823 0 : rc = -1;
1824 : }
1825 25 : if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) {
1826 24 : return -EAGAIN;
1827 : }
1828 :
1829 : /*
1830 : * For non-fabrics controllers, the memory locations of the transport qpair
1831 : * don't change when the controller is reset. They simply need to be
1832 : * re-enabled with admin commands to the controller. For fabric
1833 : * controllers we need to disconnect and reconnect the qpair on its
1834 : * own thread outside of the context of the reset.
1835 : */
1836 1 : if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
1837 : /* Reinitialize qpairs */
1838 1 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1839 : /* Always clear the qid bit here, even for a foreign qpair. We need
1840 : * to make sure another process doesn't get the chance to grab that
1841 : * qid.
1842 : */
1843 0 : assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
1844 0 : spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
1845 0 : if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) {
1846 : /*
1847 : * We cannot reinitialize a foreign qpair. The qpair's owning
1848 : * process will take care of it. Set failure reason to FAILURE_RESET
1849 : * to ensure that happens.
1850 : */
1851 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET;
1852 0 : continue;
1853 : }
1854 0 : rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair);
1855 0 : if (rc_tmp != 0) {
1856 0 : rc = rc_tmp;
1857 : }
1858 : }
1859 : }
1860 :
1861 : /*
1862 : * Take this opportunity to remove inactive namespaces. During a reset namespace
1863 : * handles can be invalidated.
1864 : */
1865 5 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
1866 4 : if (!ns->active) {
1867 1 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
1868 1 : spdk_free(ns);
1869 : }
1870 : }
1871 :
1872 1 : if (rc) {
1873 0 : nvme_ctrlr_fail(ctrlr, false);
1874 : }
1875 1 : ctrlr->is_resetting = false;
1876 :
1877 1 : nvme_ctrlr_unlock(ctrlr);
1878 :
1879 1 : if (!ctrlr->cdata.oaes.ns_attribute_notices) {
1880 : /*
1881 : * If controller doesn't support ns_attribute_notices and
1882 : * namespace attributes change (e.g. number of namespaces)
1883 : * we need to update system handling device reset.
1884 : */
1885 1 : nvme_io_msg_ctrlr_update(ctrlr);
1886 : }
1887 :
1888 1 : return rc;
1889 : }
1890 :
1891 : /*
1892 : * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset
1893 : * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair.
1894 : * The following two functions are added to do a Controller Level Reset. They have
1895 : * to be called under the nvme controller's lock.
1896 : */
1897 : void
1898 1 : nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1899 : {
1900 1 : assert(ctrlr->is_disconnecting == true);
1901 :
1902 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
1903 1 : }
1904 :
1905 : int
1906 2 : nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr)
1907 : {
1908 2 : int rc = 0;
1909 :
1910 2 : if (nvme_ctrlr_process_init(ctrlr) != 0) {
1911 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n");
1912 0 : rc = -1;
1913 : }
1914 :
1915 2 : if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) {
1916 1 : return -EAGAIN;
1917 : }
1918 :
1919 1 : return rc;
1920 : }
1921 :
1922 : static void
1923 1 : nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr)
1924 : {
1925 : struct spdk_nvme_qpair *qpair;
1926 :
1927 1 : TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1928 0 : qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1929 : }
1930 1 : }
1931 :
1932 : int
1933 2 : spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1934 : {
1935 : int rc;
1936 :
1937 2 : nvme_ctrlr_lock(ctrlr);
1938 :
1939 2 : rc = nvme_ctrlr_disconnect(ctrlr);
1940 2 : if (rc == 0) {
1941 1 : nvme_ctrlr_fail_io_qpairs(ctrlr);
1942 : }
1943 :
1944 2 : nvme_ctrlr_unlock(ctrlr);
1945 :
1946 2 : if (rc != 0) {
1947 1 : if (rc == -EBUSY) {
1948 1 : rc = 0;
1949 : }
1950 1 : return rc;
1951 : }
1952 :
1953 : while (1) {
1954 1 : rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr);
1955 1 : if (rc == -ENXIO) {
1956 1 : break;
1957 : }
1958 : }
1959 :
1960 1 : spdk_nvme_ctrlr_reconnect_async(ctrlr);
1961 :
1962 : while (true) {
1963 25 : rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr);
1964 25 : if (rc != -EAGAIN) {
1965 1 : break;
1966 : }
1967 : }
1968 :
1969 1 : return rc;
1970 : }
1971 :
1972 : int
1973 0 : spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1974 : {
1975 : union spdk_nvme_cap_register cap;
1976 0 : int rc = 0;
1977 :
1978 0 : cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1979 0 : if (cap.bits.nssrs == 0) {
1980 0 : NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n");
1981 0 : return -ENOTSUP;
1982 : }
1983 :
1984 0 : NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n");
1985 0 : nvme_ctrlr_lock(ctrlr);
1986 0 : ctrlr->is_resetting = true;
1987 0 : rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1988 0 : ctrlr->is_resetting = false;
1989 :
1990 0 : nvme_ctrlr_unlock(ctrlr);
1991 : /*
1992 : * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1993 : * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1994 : */
1995 0 : return rc;
1996 : }
1997 :
1998 : int
1999 4 : spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
2000 : {
2001 4 : int rc = 0;
2002 :
2003 4 : nvme_ctrlr_lock(ctrlr);
2004 :
2005 4 : if (ctrlr->is_failed == false) {
2006 1 : rc = -EPERM;
2007 1 : goto out;
2008 : }
2009 :
2010 3 : if (trid->trtype != ctrlr->trid.trtype) {
2011 1 : rc = -EINVAL;
2012 1 : goto out;
2013 : }
2014 :
2015 2 : if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
2016 1 : rc = -EINVAL;
2017 1 : goto out;
2018 : }
2019 :
2020 1 : ctrlr->trid = *trid;
2021 :
2022 4 : out:
2023 4 : nvme_ctrlr_unlock(ctrlr);
2024 4 : return rc;
2025 : }
2026 :
2027 : void
2028 0 : spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
2029 : spdk_nvme_remove_cb remove_cb, void *remove_ctx)
2030 : {
2031 0 : if (!spdk_process_is_primary()) {
2032 0 : return;
2033 : }
2034 :
2035 0 : nvme_ctrlr_lock(ctrlr);
2036 0 : ctrlr->remove_cb = remove_cb;
2037 0 : ctrlr->cb_ctx = remove_ctx;
2038 0 : nvme_ctrlr_unlock(ctrlr);
2039 : }
2040 :
2041 : static void
2042 16 : nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
2043 : {
2044 16 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2045 :
2046 16 : if (spdk_nvme_cpl_is_error(cpl)) {
2047 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n");
2048 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2049 0 : return;
2050 : }
2051 :
2052 : /*
2053 : * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
2054 : * controller supports.
2055 : */
2056 16 : ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
2057 16 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
2058 16 : if (ctrlr->cdata.mdts > 0) {
2059 0 : ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
2060 : ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
2061 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
2062 : }
2063 :
2064 16 : NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
2065 16 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
2066 1 : ctrlr->cntlid = ctrlr->cdata.cntlid;
2067 : } else {
2068 : /*
2069 : * Fabrics controllers should already have CNTLID from the Connect command.
2070 : *
2071 : * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
2072 : * trust the one from Connect.
2073 : */
2074 15 : if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
2075 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
2076 : ctrlr->cdata.cntlid, ctrlr->cntlid);
2077 : }
2078 : }
2079 :
2080 16 : if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2081 0 : assert(ctrlr->cdata.sgls.supported != 0x3);
2082 0 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
2083 0 : if (ctrlr->cdata.sgls.supported == 0x2) {
2084 0 : ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
2085 : }
2086 :
2087 0 : ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
2088 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges);
2089 : }
2090 :
2091 16 : if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) {
2092 0 : ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED;
2093 : }
2094 :
2095 16 : if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
2096 0 : ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
2097 : }
2098 :
2099 16 : if (ctrlr->cdata.oacs.directives) {
2100 0 : ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
2101 : }
2102 :
2103 16 : NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n",
2104 : ctrlr->cdata.fuses.compare_and_write);
2105 16 : if (ctrlr->cdata.fuses.compare_and_write) {
2106 0 : ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
2107 : }
2108 :
2109 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2110 16 : ctrlr->opts.admin_timeout_ms);
2111 : }
2112 :
2113 : static int
2114 16 : nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
2115 : {
2116 : int rc;
2117 :
2118 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
2119 16 : ctrlr->opts.admin_timeout_ms);
2120 :
2121 16 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
2122 16 : &ctrlr->cdata, sizeof(ctrlr->cdata),
2123 : nvme_ctrlr_identify_done, ctrlr);
2124 16 : if (rc != 0) {
2125 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2126 0 : return rc;
2127 : }
2128 :
2129 16 : return 0;
2130 : }
2131 :
2132 : static void
2133 0 : nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
2134 : {
2135 : struct spdk_nvme_cmds_and_effect_log_page *log_page;
2136 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
2137 :
2138 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2139 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
2140 0 : spdk_free(ctrlr->tmp_ptr);
2141 0 : ctrlr->tmp_ptr = NULL;
2142 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2143 0 : return;
2144 : }
2145 :
2146 0 : log_page = ctrlr->tmp_ptr;
2147 :
2148 0 : if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
2149 0 : ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
2150 : }
2151 0 : spdk_free(ctrlr->tmp_ptr);
2152 0 : ctrlr->tmp_ptr = NULL;
2153 :
2154 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
2155 : }
2156 :
2157 : static int
2158 0 : nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
2159 : {
2160 : int rc;
2161 :
2162 0 : assert(!ctrlr->tmp_ptr);
2163 0 : ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
2164 : SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2165 0 : if (!ctrlr->tmp_ptr) {
2166 0 : rc = -ENOMEM;
2167 0 : goto error;
2168 : }
2169 :
2170 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
2171 0 : ctrlr->opts.admin_timeout_ms);
2172 :
2173 0 : rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
2174 : 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
2175 : 0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
2176 : nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
2177 0 : if (rc != 0) {
2178 0 : goto error;
2179 : }
2180 :
2181 0 : return 0;
2182 :
2183 0 : error:
2184 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2185 0 : spdk_free(ctrlr->tmp_ptr);
2186 0 : ctrlr->tmp_ptr = NULL;
2187 0 : return rc;
2188 : }
2189 :
2190 : static void
2191 0 : nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
2192 : {
2193 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2194 :
2195 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2196 : /* no need to print an error, the controller simply does not support ZNS */
2197 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2198 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2199 0 : ctrlr->opts.admin_timeout_ms);
2200 0 : return;
2201 : }
2202 :
2203 : /* A zero zasl value means use mdts */
2204 0 : if (ctrlr->cdata_zns->zasl) {
2205 0 : uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
2206 0 : ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
2207 : } else {
2208 0 : ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
2209 : }
2210 :
2211 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
2212 0 : ctrlr->opts.admin_timeout_ms);
2213 : }
2214 :
2215 : /**
2216 : * This function will try to fetch the I/O Command Specific Controller data structure for
2217 : * each I/O Command Set supported by SPDK.
2218 : *
2219 : * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
2220 : * will be returned. Since we are fetching in a exploratively way, getting an error back
2221 : * from the controller should not be treated as fatal.
2222 : *
2223 : * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
2224 : *
2225 : * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
2226 : * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
2227 : */
2228 : static int
2229 19 : nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2230 : {
2231 : int rc;
2232 :
2233 19 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2234 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
2235 19 : ctrlr->opts.admin_timeout_ms);
2236 19 : return 0;
2237 : }
2238 :
2239 : /*
2240 : * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
2241 : * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
2242 : * which would require additional functions and complexity for no good reason.
2243 : */
2244 0 : assert(!ctrlr->cdata_zns);
2245 0 : ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2246 : SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2247 0 : if (!ctrlr->cdata_zns) {
2248 0 : rc = -ENOMEM;
2249 0 : goto error;
2250 : }
2251 :
2252 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
2253 0 : ctrlr->opts.admin_timeout_ms);
2254 :
2255 0 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
2256 0 : ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
2257 : nvme_ctrlr_identify_zns_specific_done, ctrlr);
2258 0 : if (rc != 0) {
2259 0 : goto error;
2260 : }
2261 :
2262 0 : return 0;
2263 :
2264 0 : error:
2265 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2266 0 : nvme_ctrlr_free_zns_specific_data(ctrlr);
2267 0 : return rc;
2268 : }
2269 :
2270 : enum nvme_active_ns_state {
2271 : NVME_ACTIVE_NS_STATE_IDLE,
2272 : NVME_ACTIVE_NS_STATE_PROCESSING,
2273 : NVME_ACTIVE_NS_STATE_DONE,
2274 : NVME_ACTIVE_NS_STATE_ERROR
2275 : };
2276 :
2277 : typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
2278 :
2279 : struct nvme_active_ns_ctx {
2280 : struct spdk_nvme_ctrlr *ctrlr;
2281 : uint32_t page_count;
2282 : uint32_t next_nsid;
2283 : uint32_t *new_ns_list;
2284 : nvme_active_ns_ctx_deleter deleter;
2285 :
2286 : enum nvme_active_ns_state state;
2287 : };
2288 :
2289 : static struct nvme_active_ns_ctx *
2290 45 : nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
2291 : {
2292 : struct nvme_active_ns_ctx *ctx;
2293 45 : uint32_t *new_ns_list = NULL;
2294 :
2295 45 : ctx = calloc(1, sizeof(*ctx));
2296 45 : if (!ctx) {
2297 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n");
2298 0 : return NULL;
2299 : }
2300 :
2301 45 : new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
2302 : NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE);
2303 45 : if (!new_ns_list) {
2304 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n");
2305 0 : free(ctx);
2306 0 : return NULL;
2307 : }
2308 :
2309 45 : ctx->page_count = 1;
2310 45 : ctx->new_ns_list = new_ns_list;
2311 45 : ctx->ctrlr = ctrlr;
2312 45 : ctx->deleter = deleter;
2313 :
2314 45 : return ctx;
2315 : }
2316 :
2317 : static void
2318 45 : nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
2319 : {
2320 45 : spdk_free(ctx->new_ns_list);
2321 45 : free(ctx);
2322 45 : }
2323 :
2324 : static int
2325 18403 : nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2326 : {
2327 18403 : struct spdk_nvme_ns tmp, *ns;
2328 :
2329 18403 : assert(ctrlr != NULL);
2330 :
2331 18403 : tmp.id = nsid;
2332 18403 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
2333 18403 : if (ns == NULL) {
2334 0 : return -EINVAL;
2335 : }
2336 :
2337 18403 : nvme_ns_destruct(ns);
2338 18403 : ns->active = false;
2339 :
2340 18403 : return 0;
2341 : }
2342 :
2343 : static int
2344 12311 : nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
2345 : {
2346 : struct spdk_nvme_ns *ns;
2347 :
2348 12311 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
2349 0 : return -EINVAL;
2350 : }
2351 :
2352 : /* Namespaces are constructed on demand, so simply request it. */
2353 12311 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2354 12311 : if (ns == NULL) {
2355 0 : return -ENOMEM;
2356 : }
2357 :
2358 12311 : ns->active = true;
2359 :
2360 12311 : return 0;
2361 : }
2362 :
2363 : static void
2364 44 : nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list,
2365 : size_t max_entries)
2366 : {
2367 44 : uint32_t active_ns_count = 0;
2368 : size_t i;
2369 : uint32_t nsid;
2370 : struct spdk_nvme_ns *ns, *tmp_ns;
2371 : int rc;
2372 :
2373 : /* First, remove namespaces that no longer exist */
2374 15387 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
2375 15343 : nsid = new_ns_list[0];
2376 15343 : active_ns_count = 0;
2377 3547429 : while (nsid != 0) {
2378 3536712 : if (nsid == ns->id) {
2379 4626 : break;
2380 : }
2381 :
2382 3532086 : nsid = new_ns_list[active_ns_count++];
2383 : }
2384 :
2385 15343 : if (nsid != ns->id) {
2386 : /* Did not find this namespace id in the new list. */
2387 10717 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id);
2388 10717 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
2389 : }
2390 : }
2391 :
2392 : /* Next, add new namespaces */
2393 44 : active_ns_count = 0;
2394 12355 : for (i = 0; i < max_entries; i++) {
2395 12355 : nsid = new_ns_list[active_ns_count];
2396 :
2397 12355 : if (nsid == 0) {
2398 44 : break;
2399 : }
2400 :
2401 : /* If the namespace already exists, this will not construct it a second time. */
2402 12311 : rc = nvme_ctrlr_construct_namespace(ctrlr, nsid);
2403 12311 : if (rc != 0) {
2404 : /* We can't easily handle a failure here. But just move on. */
2405 0 : assert(false);
2406 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n");
2407 : continue;
2408 : }
2409 :
2410 12311 : active_ns_count++;
2411 : }
2412 :
2413 44 : ctrlr->active_ns_count = active_ns_count;
2414 44 : }
2415 :
2416 : static void
2417 30 : nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2418 : {
2419 30 : struct nvme_active_ns_ctx *ctx = arg;
2420 30 : uint32_t *new_ns_list = NULL;
2421 :
2422 30 : if (spdk_nvme_cpl_is_error(cpl)) {
2423 1 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2424 1 : goto out;
2425 : }
2426 :
2427 29 : ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1];
2428 29 : if (ctx->next_nsid == 0) {
2429 24 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2430 24 : goto out;
2431 : }
2432 :
2433 5 : ctx->page_count++;
2434 5 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2435 5 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2436 5 : ctx->ctrlr->page_size);
2437 5 : if (!new_ns_list) {
2438 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2439 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2440 0 : goto out;
2441 : }
2442 :
2443 5 : ctx->new_ns_list = new_ns_list;
2444 5 : nvme_ctrlr_identify_active_ns_async(ctx);
2445 5 : return;
2446 :
2447 25 : out:
2448 25 : if (ctx->deleter) {
2449 9 : ctx->deleter(ctx);
2450 : }
2451 : }
2452 :
2453 : static void
2454 50 : nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
2455 : {
2456 50 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2457 : uint32_t i;
2458 : int rc;
2459 :
2460 50 : if (ctrlr->cdata.nn == 0) {
2461 16 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2462 16 : goto out;
2463 : }
2464 :
2465 34 : assert(ctx->new_ns_list != NULL);
2466 :
2467 : /*
2468 : * If controller doesn't support active ns list CNS 0x02 dummy up
2469 : * an active ns list, i.e. all namespaces report as active
2470 : */
2471 34 : if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
2472 : uint32_t *new_ns_list;
2473 :
2474 : /*
2475 : * Active NS list must always end with zero element.
2476 : * So, we allocate for cdata.nn+1.
2477 : */
2478 4 : ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1,
2479 : sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0]));
2480 4 : new_ns_list = spdk_realloc(ctx->new_ns_list,
2481 4 : ctx->page_count * sizeof(struct spdk_nvme_ns_list),
2482 4 : ctx->ctrlr->page_size);
2483 4 : if (!new_ns_list) {
2484 0 : SPDK_ERRLOG("Failed to reallocate active_ns_list!\n");
2485 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2486 0 : goto out;
2487 : }
2488 :
2489 4 : ctx->new_ns_list = new_ns_list;
2490 4 : ctx->new_ns_list[ctrlr->cdata.nn] = 0;
2491 4091 : for (i = 0; i < ctrlr->cdata.nn; i++) {
2492 4087 : ctx->new_ns_list[i] = i + 1;
2493 : }
2494 :
2495 4 : ctx->state = NVME_ACTIVE_NS_STATE_DONE;
2496 4 : goto out;
2497 : }
2498 :
2499 30 : ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
2500 30 : rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
2501 30 : &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list),
2502 : nvme_ctrlr_identify_active_ns_async_done, ctx);
2503 30 : if (rc != 0) {
2504 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2505 0 : goto out;
2506 : }
2507 :
2508 30 : return;
2509 :
2510 20 : out:
2511 20 : if (ctx->deleter) {
2512 15 : ctx->deleter(ctx);
2513 : }
2514 : }
2515 :
2516 : static void
2517 24 : _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
2518 : {
2519 24 : struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
2520 : struct spdk_nvme_ns *ns;
2521 :
2522 24 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2523 0 : nvme_active_ns_ctx_destroy(ctx);
2524 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2525 0 : return;
2526 : }
2527 :
2528 24 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2529 :
2530 28 : RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) {
2531 4 : nvme_ns_free_iocs_specific_data(ns);
2532 : }
2533 :
2534 24 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2535 24 : nvme_active_ns_ctx_destroy(ctx);
2536 24 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
2537 : }
2538 :
2539 : static void
2540 24 : _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2541 : {
2542 : struct nvme_active_ns_ctx *ctx;
2543 :
2544 24 : ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
2545 24 : if (!ctx) {
2546 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2547 0 : return;
2548 : }
2549 :
2550 24 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
2551 24 : ctrlr->opts.admin_timeout_ms);
2552 24 : nvme_ctrlr_identify_active_ns_async(ctx);
2553 : }
2554 :
2555 : int
2556 21 : nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
2557 : {
2558 : struct nvme_active_ns_ctx *ctx;
2559 : int rc;
2560 :
2561 21 : ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
2562 21 : if (!ctx) {
2563 0 : return -ENOMEM;
2564 : }
2565 :
2566 21 : nvme_ctrlr_identify_active_ns_async(ctx);
2567 21 : while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
2568 0 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
2569 0 : if (rc < 0) {
2570 0 : ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
2571 0 : break;
2572 : }
2573 : }
2574 :
2575 21 : if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
2576 1 : nvme_active_ns_ctx_destroy(ctx);
2577 1 : return -ENXIO;
2578 : }
2579 :
2580 20 : assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
2581 20 : nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024);
2582 20 : nvme_active_ns_ctx_destroy(ctx);
2583 :
2584 20 : return 0;
2585 : }
2586 :
2587 : static void
2588 21 : nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2589 : {
2590 21 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2591 21 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2592 : uint32_t nsid;
2593 : int rc;
2594 :
2595 21 : if (spdk_nvme_cpl_is_error(cpl)) {
2596 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2597 0 : return;
2598 : }
2599 :
2600 21 : nvme_ns_set_identify_data(ns);
2601 :
2602 : /* move on to the next active NS */
2603 21 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2604 21 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2605 21 : if (ns == NULL) {
2606 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2607 6 : ctrlr->opts.admin_timeout_ms);
2608 6 : return;
2609 : }
2610 15 : ns->ctrlr = ctrlr;
2611 15 : ns->id = nsid;
2612 :
2613 15 : rc = nvme_ctrlr_identify_ns_async(ns);
2614 15 : if (rc) {
2615 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2616 : }
2617 : }
2618 :
2619 : static int
2620 21 : nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
2621 : {
2622 21 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2623 : struct spdk_nvme_ns_data *nsdata;
2624 :
2625 21 : nsdata = &ns->nsdata;
2626 :
2627 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
2628 21 : ctrlr->opts.admin_timeout_ms);
2629 21 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
2630 : nsdata, sizeof(*nsdata),
2631 : nvme_ctrlr_identify_ns_async_done, ns);
2632 : }
2633 :
2634 : static int
2635 14 : nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2636 : {
2637 : uint32_t nsid;
2638 : struct spdk_nvme_ns *ns;
2639 : int rc;
2640 :
2641 14 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2642 14 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2643 14 : if (ns == NULL) {
2644 : /* No active NS, move on to the next state */
2645 8 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
2646 8 : ctrlr->opts.admin_timeout_ms);
2647 8 : return 0;
2648 : }
2649 :
2650 6 : ns->ctrlr = ctrlr;
2651 6 : ns->id = nsid;
2652 :
2653 6 : rc = nvme_ctrlr_identify_ns_async(ns);
2654 6 : if (rc) {
2655 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2656 : }
2657 :
2658 6 : return rc;
2659 : }
2660 :
2661 : static int
2662 4 : nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2663 : {
2664 : uint32_t nsid;
2665 : struct spdk_nvme_ns *ns;
2666 : int rc;
2667 :
2668 4 : if (!prev_nsid) {
2669 2 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2670 : } else {
2671 : /* move on to the next active NS */
2672 2 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2673 : }
2674 :
2675 4 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2676 4 : if (ns == NULL) {
2677 : /* No first/next active NS, move on to the next state */
2678 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2679 1 : ctrlr->opts.admin_timeout_ms);
2680 1 : return 0;
2681 : }
2682 :
2683 : /* loop until we find a ns which has (supported) iocs specific data */
2684 10 : while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2685 8 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2686 8 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2687 8 : if (ns == NULL) {
2688 : /* no namespace with (supported) iocs specific data found */
2689 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2690 1 : ctrlr->opts.admin_timeout_ms);
2691 1 : return 0;
2692 : }
2693 : }
2694 :
2695 2 : rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2696 2 : if (rc) {
2697 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2698 : }
2699 :
2700 2 : return rc;
2701 : }
2702 :
2703 : static void
2704 0 : nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2705 : {
2706 0 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2707 0 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2708 :
2709 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2710 0 : nvme_ns_free_zns_specific_data(ns);
2711 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2712 0 : return;
2713 : }
2714 :
2715 0 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2716 : }
2717 :
2718 : static int
2719 2 : nvme_ctrlr_identify_ns_zns_specific_async(struct spdk_nvme_ns *ns)
2720 : {
2721 2 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2722 : int rc;
2723 :
2724 2 : assert(!ns->nsdata_zns);
2725 2 : ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2726 : SPDK_MALLOC_SHARE);
2727 2 : if (!ns->nsdata_zns) {
2728 0 : return -ENOMEM;
2729 : }
2730 :
2731 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2732 2 : ctrlr->opts.admin_timeout_ms);
2733 2 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
2734 2 : ns->nsdata_zns, sizeof(*ns->nsdata_zns),
2735 : nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2736 2 : if (rc) {
2737 1 : nvme_ns_free_zns_specific_data(ns);
2738 : }
2739 :
2740 2 : return rc;
2741 : }
2742 :
2743 : static void
2744 0 : nvme_ctrlr_identify_ns_nvm_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2745 : {
2746 0 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2747 0 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2748 :
2749 0 : if (spdk_nvme_cpl_is_error(cpl)) {
2750 0 : nvme_ns_free_nvm_specific_data(ns);
2751 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2752 0 : return;
2753 : }
2754 :
2755 0 : nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2756 : }
2757 :
2758 : static int
2759 0 : nvme_ctrlr_identify_ns_nvm_specific_async(struct spdk_nvme_ns *ns)
2760 : {
2761 0 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2762 : int rc;
2763 :
2764 0 : assert(!ns->nsdata_nvm);
2765 0 : ns->nsdata_nvm = spdk_zmalloc(sizeof(*ns->nsdata_nvm), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2766 : SPDK_MALLOC_SHARE);
2767 0 : if (!ns->nsdata_nvm) {
2768 0 : return -ENOMEM;
2769 : }
2770 :
2771 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2772 0 : ctrlr->opts.admin_timeout_ms);
2773 0 : rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
2774 0 : ns->nsdata_nvm, sizeof(*ns->nsdata_nvm),
2775 : nvme_ctrlr_identify_ns_nvm_specific_async_done, ns);
2776 0 : if (rc) {
2777 0 : nvme_ns_free_nvm_specific_data(ns);
2778 : }
2779 :
2780 0 : return rc;
2781 : }
2782 :
2783 : static int
2784 2 : nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2785 : {
2786 2 : switch (ns->csi) {
2787 2 : case SPDK_NVME_CSI_ZNS:
2788 2 : return nvme_ctrlr_identify_ns_zns_specific_async(ns);
2789 0 : case SPDK_NVME_CSI_NVM:
2790 0 : if (ns->ctrlr->cdata.ctratt.bits.elbas) {
2791 0 : return nvme_ctrlr_identify_ns_nvm_specific_async(ns);
2792 : }
2793 : /* fallthrough */
2794 : default:
2795 : /*
2796 : * This switch must handle all cases for which
2797 : * nvme_ns_has_supported_iocs_specific_data() returns true,
2798 : * other cases should never happen.
2799 : */
2800 0 : assert(0);
2801 : }
2802 :
2803 : return -EINVAL;
2804 : }
2805 :
2806 : static int
2807 14 : nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2808 : {
2809 14 : if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2810 : /* Multi IOCS not supported/enabled, move on to the next state */
2811 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2812 14 : ctrlr->opts.admin_timeout_ms);
2813 14 : return 0;
2814 : }
2815 :
2816 0 : return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2817 : }
2818 :
2819 : static void
2820 6 : nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2821 : {
2822 6 : struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2823 6 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2824 : uint32_t nsid;
2825 : int rc;
2826 :
2827 6 : if (spdk_nvme_cpl_is_error(cpl)) {
2828 : /*
2829 : * Many controllers claim to be compatible with NVMe 1.3, however,
2830 : * they do not implement NS ID Desc List. Therefore, instead of setting
2831 : * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion
2832 : * error and move on to the next state.
2833 : *
2834 : * The proper way is to create a new quirk for controllers that violate
2835 : * the NVMe 1.3 spec by not supporting NS ID Desc List.
2836 : * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since
2837 : * it is too generic and was added in order to handle controllers that
2838 : * violate the NVMe 1.1 spec by not supporting ACTIVE LIST).
2839 : */
2840 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2841 0 : ctrlr->opts.admin_timeout_ms);
2842 0 : return;
2843 : }
2844 :
2845 6 : nvme_ns_set_id_desc_list_data(ns);
2846 :
2847 : /* move on to the next active NS */
2848 6 : nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2849 6 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2850 6 : if (ns == NULL) {
2851 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2852 2 : ctrlr->opts.admin_timeout_ms);
2853 2 : return;
2854 : }
2855 :
2856 4 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2857 4 : if (rc) {
2858 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2859 : }
2860 : }
2861 :
2862 : static int
2863 6 : nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2864 : {
2865 6 : struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2866 :
2867 6 : memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2868 :
2869 6 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2870 6 : ctrlr->opts.admin_timeout_ms);
2871 12 : return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2872 6 : 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
2873 : nvme_ctrlr_identify_id_desc_async_done, ns);
2874 : }
2875 :
2876 : static int
2877 14 : nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2878 : {
2879 : uint32_t nsid;
2880 : struct spdk_nvme_ns *ns;
2881 : int rc;
2882 :
2883 14 : if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
2884 12 : !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
2885 2 : (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2886 12 : NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
2887 : /* NS ID Desc List not supported, move on to the next state */
2888 12 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2889 12 : ctrlr->opts.admin_timeout_ms);
2890 12 : return 0;
2891 : }
2892 :
2893 2 : nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2894 2 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2895 2 : if (ns == NULL) {
2896 : /* No active NS, move on to the next state */
2897 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2898 0 : ctrlr->opts.admin_timeout_ms);
2899 0 : return 0;
2900 : }
2901 :
2902 2 : rc = nvme_ctrlr_identify_id_desc_async(ns);
2903 2 : if (rc) {
2904 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2905 : }
2906 :
2907 2 : return rc;
2908 : }
2909 :
2910 : static void
2911 19 : nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2912 : {
2913 19 : if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) {
2914 4 : if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
2915 0 : NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n",
2916 : ctrlr->cdata.nvmf_specific.ioccsz);
2917 0 : ctrlr->cdata.nvmf_specific.ioccsz = 4;
2918 0 : assert(0);
2919 : }
2920 4 : ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
2921 4 : ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
2922 : }
2923 19 : }
2924 :
2925 : static void
2926 19 : nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2927 : {
2928 : uint32_t cq_allocated, sq_allocated, min_allocated, i;
2929 19 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2930 :
2931 19 : if (spdk_nvme_cpl_is_error(cpl)) {
2932 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n");
2933 0 : ctrlr->opts.num_io_queues = 0;
2934 : } else {
2935 : /*
2936 : * Data in cdw0 is 0-based.
2937 : * Lower 16-bits indicate number of submission queues allocated.
2938 : * Upper 16-bits indicate number of completion queues allocated.
2939 : */
2940 19 : sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2941 19 : cq_allocated = (cpl->cdw0 >> 16) + 1;
2942 :
2943 : /*
2944 : * For 1:1 queue mapping, set number of allocated queues to be minimum of
2945 : * submission and completion queues.
2946 : */
2947 19 : min_allocated = spdk_min(sq_allocated, cq_allocated);
2948 :
2949 : /* Set number of queues to be minimum of requested and actually allocated. */
2950 19 : ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
2951 : }
2952 :
2953 19 : ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
2954 19 : if (ctrlr->free_io_qids == NULL) {
2955 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2956 0 : return;
2957 : }
2958 :
2959 : /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2960 69 : for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
2961 50 : spdk_nvme_ctrlr_free_qid(ctrlr, i);
2962 : }
2963 :
2964 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
2965 19 : ctrlr->opts.admin_timeout_ms);
2966 : }
2967 :
2968 : static int
2969 19 : nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2970 : {
2971 : int rc;
2972 :
2973 19 : if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
2974 0 : NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n",
2975 : ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2976 0 : ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
2977 19 : } else if (ctrlr->opts.num_io_queues < 1) {
2978 13 : NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n");
2979 13 : ctrlr->opts.num_io_queues = 1;
2980 : }
2981 :
2982 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2983 19 : ctrlr->opts.admin_timeout_ms);
2984 :
2985 19 : rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
2986 : nvme_ctrlr_set_num_queues_done, ctrlr);
2987 19 : if (rc != 0) {
2988 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2989 0 : return rc;
2990 : }
2991 :
2992 19 : return 0;
2993 : }
2994 :
2995 : static void
2996 3 : nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2997 : {
2998 : uint32_t keep_alive_interval_us;
2999 3 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3000 :
3001 3 : if (spdk_nvme_cpl_is_error(cpl)) {
3002 2 : if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
3003 2 : (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
3004 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n");
3005 : } else {
3006 1 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n",
3007 : cpl->status.sc, cpl->status.sct);
3008 1 : ctrlr->opts.keep_alive_timeout_ms = 0;
3009 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3010 1 : return;
3011 : }
3012 : } else {
3013 1 : if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
3014 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n",
3015 : cpl->cdw0);
3016 : }
3017 :
3018 1 : ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
3019 : }
3020 :
3021 2 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
3022 0 : ctrlr->keep_alive_interval_ticks = 0;
3023 : } else {
3024 2 : keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
3025 :
3026 2 : NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us);
3027 :
3028 2 : ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
3029 : UINT64_C(1000000);
3030 :
3031 : /* Schedule the first Keep Alive to be sent as soon as possible. */
3032 2 : ctrlr->next_keep_alive_tick = spdk_get_ticks();
3033 : }
3034 :
3035 2 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3036 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
3037 : } else {
3038 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
3039 2 : ctrlr->opts.admin_timeout_ms);
3040 : }
3041 : }
3042 :
3043 : static int
3044 22 : nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
3045 : {
3046 : int rc;
3047 :
3048 22 : if (ctrlr->opts.keep_alive_timeout_ms == 0) {
3049 19 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3050 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
3051 : } else {
3052 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
3053 19 : ctrlr->opts.admin_timeout_ms);
3054 : }
3055 19 : return 0;
3056 : }
3057 :
3058 : /* Note: Discovery controller identify data does not populate KAS according to spec. */
3059 3 : if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) {
3060 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n");
3061 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
3062 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
3063 0 : ctrlr->opts.admin_timeout_ms);
3064 0 : return 0;
3065 : }
3066 :
3067 3 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
3068 3 : ctrlr->opts.admin_timeout_ms);
3069 :
3070 : /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
3071 3 : rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
3072 : nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
3073 3 : if (rc != 0) {
3074 0 : NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc);
3075 0 : ctrlr->opts.keep_alive_timeout_ms = 0;
3076 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3077 0 : return rc;
3078 : }
3079 :
3080 3 : return 0;
3081 : }
3082 :
3083 : static void
3084 0 : nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
3085 : {
3086 0 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3087 :
3088 0 : if (spdk_nvme_cpl_is_error(cpl)) {
3089 : /*
3090 : * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
3091 : * is optional.
3092 : */
3093 0 : NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
3094 : cpl->status.sc, cpl->status.sct);
3095 : } else {
3096 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n");
3097 : }
3098 :
3099 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
3100 0 : }
3101 :
3102 : static int
3103 14 : nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
3104 : {
3105 : uint8_t *host_id;
3106 : uint32_t host_id_size;
3107 : int rc;
3108 :
3109 14 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
3110 : /*
3111 : * NVMe-oF sends the host ID during Connect and doesn't allow
3112 : * Set Features - Host Identifier after Connect, so we don't need to do anything here.
3113 : */
3114 14 : NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n");
3115 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
3116 14 : return 0;
3117 : }
3118 :
3119 0 : if (ctrlr->cdata.ctratt.bits.host_id_exhid_supported) {
3120 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n");
3121 0 : host_id = ctrlr->opts.extended_host_id;
3122 0 : host_id_size = sizeof(ctrlr->opts.extended_host_id);
3123 : } else {
3124 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n");
3125 0 : host_id = ctrlr->opts.host_id;
3126 0 : host_id_size = sizeof(ctrlr->opts.host_id);
3127 : }
3128 :
3129 : /* If the user specified an all-zeroes host identifier, don't send the command. */
3130 0 : if (spdk_mem_all_zero(host_id, host_id_size)) {
3131 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n");
3132 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms);
3133 0 : return 0;
3134 : }
3135 :
3136 0 : SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
3137 :
3138 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
3139 0 : ctrlr->opts.admin_timeout_ms);
3140 :
3141 0 : rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
3142 0 : if (rc != 0) {
3143 0 : NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc);
3144 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3145 0 : return rc;
3146 : }
3147 :
3148 0 : return 0;
3149 : }
3150 :
3151 : void
3152 4 : nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
3153 : {
3154 : uint32_t nsid;
3155 : struct spdk_nvme_ns *ns;
3156 :
3157 4 : for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
3158 19 : nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) {
3159 15 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
3160 15 : nvme_ns_construct(ns, nsid, ctrlr);
3161 : }
3162 4 : }
3163 :
3164 : static int
3165 4 : nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr)
3166 : {
3167 : struct nvme_completion_poll_status *status;
3168 4 : int rc = -ENOMEM;
3169 4 : char *buffer = NULL;
3170 : uint32_t nsid;
3171 4 : size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t));
3172 :
3173 4 : if (ctrlr->opts.disable_read_changed_ns_list_log_page) {
3174 0 : return 0;
3175 : }
3176 :
3177 4 : buffer = spdk_dma_zmalloc(buf_size, 4096, NULL);
3178 4 : if (!buffer) {
3179 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting "
3180 : "changed ns log.\n");
3181 0 : return rc;
3182 : }
3183 :
3184 4 : status = calloc(1, sizeof(*status));
3185 4 : if (!status) {
3186 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
3187 0 : goto free_buffer;
3188 : }
3189 :
3190 4 : rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr,
3191 : SPDK_NVME_LOG_CHANGED_NS_LIST,
3192 : SPDK_NVME_GLOBAL_NS_TAG,
3193 : buffer, buf_size, 0,
3194 : nvme_completion_poll_cb, status);
3195 :
3196 4 : if (rc) {
3197 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc);
3198 0 : free(status);
3199 0 : goto free_buffer;
3200 : }
3201 :
3202 4 : rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status,
3203 4 : ctrlr->opts.admin_timeout_ms * 1000);
3204 4 : if (!status->timed_out) {
3205 4 : free(status);
3206 : }
3207 :
3208 4 : if (rc) {
3209 0 : NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc);
3210 0 : goto free_buffer;
3211 : }
3212 :
3213 : /* only check the case of overflow. */
3214 4 : nsid = from_le32(buffer);
3215 4 : if (nsid == 0xffffffffu) {
3216 0 : NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n");
3217 : }
3218 :
3219 4 : free_buffer:
3220 4 : spdk_dma_free(buffer);
3221 4 : return rc;
3222 : }
3223 :
3224 : static void
3225 5 : nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr,
3226 : const struct spdk_nvme_cpl *cpl)
3227 : {
3228 : union spdk_nvme_async_event_completion event;
3229 : struct spdk_nvme_ctrlr_process *active_proc;
3230 : int rc;
3231 :
3232 5 : event.raw = cpl->cdw0;
3233 :
3234 5 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3235 5 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
3236 4 : nvme_ctrlr_clear_changed_ns_log(ctrlr);
3237 :
3238 4 : rc = nvme_ctrlr_identify_active_ns(ctrlr);
3239 4 : if (rc) {
3240 0 : return;
3241 : }
3242 4 : nvme_ctrlr_update_namespaces(ctrlr);
3243 4 : nvme_io_msg_ctrlr_update(ctrlr);
3244 : }
3245 :
3246 5 : if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
3247 5 : (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
3248 1 : if (!ctrlr->opts.disable_read_ana_log_page) {
3249 1 : rc = nvme_ctrlr_update_ana_log_page(ctrlr);
3250 1 : if (rc) {
3251 0 : return;
3252 : }
3253 1 : nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
3254 : ctrlr);
3255 : }
3256 : }
3257 :
3258 5 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3259 5 : if (active_proc && active_proc->aer_cb_fn) {
3260 3 : active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
3261 : }
3262 : }
3263 :
3264 : static void
3265 5 : nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr,
3266 : const struct spdk_nvme_cpl *cpl)
3267 : {
3268 : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event;
3269 : struct spdk_nvme_ctrlr_process *proc;
3270 :
3271 : /* Add async event to each process objects event list */
3272 10 : TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) {
3273 : /* Must be shared memory so other processes can access */
3274 5 : nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3275 5 : if (!nvme_event) {
3276 0 : NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n");
3277 0 : return;
3278 : }
3279 5 : nvme_event->cpl = *cpl;
3280 :
3281 5 : STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link);
3282 : }
3283 : }
3284 :
3285 : static void
3286 5 : nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr)
3287 : {
3288 : struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp;
3289 : struct spdk_nvme_ctrlr_process *active_proc;
3290 :
3291 5 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3292 :
3293 10 : STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) {
3294 5 : STAILQ_REMOVE(&active_proc->async_events, nvme_event,
3295 : spdk_nvme_ctrlr_aer_completion_list, link);
3296 5 : nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl);
3297 5 : spdk_free(nvme_event);
3298 :
3299 : }
3300 5 : }
3301 :
3302 : static void
3303 5 : nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
3304 : {
3305 5 : struct nvme_async_event_request *aer = arg;
3306 5 : struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr;
3307 :
3308 5 : if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
3309 5 : cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
3310 : /*
3311 : * This is simulated when controller is being shut down, to
3312 : * effectively abort outstanding asynchronous event requests
3313 : * and make sure all memory is freed. Do not repost the
3314 : * request in this case.
3315 : */
3316 0 : return;
3317 : }
3318 :
3319 5 : if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
3320 0 : cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
3321 : /*
3322 : * SPDK will only send as many AERs as the device says it supports,
3323 : * so this status code indicates an out-of-spec device. Do not repost
3324 : * the request in this case.
3325 : */
3326 0 : NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n"
3327 : "handling. Do not repost this AER.\n");
3328 0 : return;
3329 : }
3330 :
3331 : /* Add the events to the list */
3332 5 : nvme_ctrlr_queue_async_event(ctrlr, cpl);
3333 :
3334 : /* If the ctrlr was removed or in the destruct state, we should not send aer again */
3335 5 : if (ctrlr->is_removed || ctrlr->is_destructed) {
3336 0 : return;
3337 : }
3338 :
3339 : /*
3340 : * Repost another asynchronous event request to replace the one
3341 : * that just completed.
3342 : */
3343 5 : if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
3344 : /*
3345 : * We can't do anything to recover from a failure here,
3346 : * so just print a warning message and leave the AER unsubmitted.
3347 : */
3348 0 : NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n");
3349 : }
3350 : }
3351 :
3352 : static int
3353 24 : nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
3354 : struct nvme_async_event_request *aer)
3355 : {
3356 : struct nvme_request *req;
3357 :
3358 24 : aer->ctrlr = ctrlr;
3359 24 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
3360 24 : aer->req = req;
3361 24 : if (req == NULL) {
3362 0 : return -1;
3363 : }
3364 :
3365 24 : req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
3366 24 : return nvme_ctrlr_submit_admin_request(ctrlr, req);
3367 : }
3368 :
3369 : static void
3370 19 : nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
3371 : {
3372 : struct nvme_async_event_request *aer;
3373 : int rc;
3374 : uint32_t i;
3375 19 : struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
3376 :
3377 19 : if (spdk_nvme_cpl_is_error(cpl)) {
3378 0 : NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n");
3379 0 : ctrlr->num_aers = 0;
3380 : } else {
3381 : /* aerl is a zero-based value, so we need to add 1 here. */
3382 19 : ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
3383 : }
3384 :
3385 38 : for (i = 0; i < ctrlr->num_aers; i++) {
3386 19 : aer = &ctrlr->aer[i];
3387 19 : rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
3388 19 : if (rc) {
3389 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n");
3390 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3391 0 : return;
3392 : }
3393 : }
3394 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms);
3395 : }
3396 :
3397 : static int
3398 19 : nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
3399 : {
3400 : union spdk_nvme_feat_async_event_configuration config;
3401 : int rc;
3402 :
3403 19 : config.raw = 0;
3404 :
3405 19 : if (spdk_nvme_ctrlr_is_discovery(ctrlr)) {
3406 0 : config.bits.discovery_log_change_notice = 1;
3407 : } else {
3408 19 : config.bits.crit_warn.bits.available_spare = 1;
3409 19 : config.bits.crit_warn.bits.temperature = 1;
3410 19 : config.bits.crit_warn.bits.device_reliability = 1;
3411 19 : config.bits.crit_warn.bits.read_only = 1;
3412 19 : config.bits.crit_warn.bits.volatile_memory_backup = 1;
3413 :
3414 19 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
3415 4 : if (ctrlr->cdata.oaes.ns_attribute_notices) {
3416 0 : config.bits.ns_attr_notice = 1;
3417 : }
3418 4 : if (ctrlr->cdata.oaes.fw_activation_notices) {
3419 0 : config.bits.fw_activation_notice = 1;
3420 : }
3421 4 : if (ctrlr->cdata.oaes.ana_change_notices) {
3422 0 : config.bits.ana_change_notice = 1;
3423 : }
3424 : }
3425 19 : if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
3426 0 : config.bits.telemetry_log_notice = 1;
3427 : }
3428 : }
3429 :
3430 19 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
3431 19 : ctrlr->opts.admin_timeout_ms);
3432 :
3433 19 : rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
3434 : nvme_ctrlr_configure_aer_done,
3435 : ctrlr);
3436 19 : if (rc != 0) {
3437 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3438 0 : return rc;
3439 : }
3440 :
3441 19 : return 0;
3442 : }
3443 :
3444 : struct spdk_nvme_ctrlr_process *
3445 61 : nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
3446 : {
3447 : struct spdk_nvme_ctrlr_process *active_proc;
3448 :
3449 61 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3450 12 : if (active_proc->pid == pid) {
3451 12 : return active_proc;
3452 : }
3453 : }
3454 :
3455 49 : return NULL;
3456 : }
3457 :
3458 : struct spdk_nvme_ctrlr_process *
3459 57 : nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
3460 : {
3461 57 : return nvme_ctrlr_get_process(ctrlr, getpid());
3462 : }
3463 :
3464 : /**
3465 : * This function will be called when a process is using the controller.
3466 : * 1. For the primary process, it is called when constructing the controller.
3467 : * 2. For the secondary process, it is called at probing the controller.
3468 : * Note: will check whether the process is already added for the same process.
3469 : */
3470 : int
3471 4 : nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
3472 : {
3473 : struct spdk_nvme_ctrlr_process *ctrlr_proc;
3474 4 : pid_t pid = getpid();
3475 :
3476 : /* Check whether the process is already added or not */
3477 4 : if (nvme_ctrlr_get_process(ctrlr, pid)) {
3478 0 : return 0;
3479 : }
3480 :
3481 : /* Initialize the per process properties for this ctrlr */
3482 4 : ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
3483 : 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
3484 4 : if (ctrlr_proc == NULL) {
3485 0 : NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n");
3486 :
3487 0 : return -1;
3488 : }
3489 :
3490 4 : ctrlr_proc->is_primary = spdk_process_is_primary();
3491 4 : ctrlr_proc->pid = pid;
3492 4 : STAILQ_INIT(&ctrlr_proc->active_reqs);
3493 4 : ctrlr_proc->devhandle = devhandle;
3494 4 : ctrlr_proc->ref = 0;
3495 4 : TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
3496 4 : STAILQ_INIT(&ctrlr_proc->async_events);
3497 :
3498 4 : TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
3499 :
3500 4 : return 0;
3501 : }
3502 :
3503 : /**
3504 : * This function will be called when the process detaches the controller.
3505 : * Note: the ctrlr_lock must be held when calling this function.
3506 : */
3507 : static void
3508 1 : nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
3509 : struct spdk_nvme_ctrlr_process *proc)
3510 : {
3511 : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3512 :
3513 1 : assert(STAILQ_EMPTY(&proc->active_reqs));
3514 :
3515 1 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3516 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3517 : }
3518 :
3519 1 : TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
3520 :
3521 1 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
3522 1 : spdk_pci_device_detach(proc->devhandle);
3523 : }
3524 :
3525 1 : spdk_free(proc);
3526 1 : }
3527 :
3528 : /**
3529 : * This function will be called when the process exited unexpectedly
3530 : * in order to free any incomplete nvme request, allocated IO qpairs
3531 : * and allocated memory.
3532 : * Note: the ctrlr_lock must be held when calling this function.
3533 : */
3534 : static void
3535 0 : nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
3536 : {
3537 : struct nvme_request *req, *tmp_req;
3538 : struct spdk_nvme_qpair *qpair, *tmp_qpair;
3539 : struct spdk_nvme_ctrlr_aer_completion_list *event;
3540 :
3541 0 : STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
3542 0 : STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
3543 :
3544 0 : assert(req->pid == proc->pid);
3545 0 : nvme_cleanup_user_req(req);
3546 0 : nvme_free_request(req);
3547 : }
3548 :
3549 : /* Remove async event from each process objects event list */
3550 0 : while (!STAILQ_EMPTY(&proc->async_events)) {
3551 0 : event = STAILQ_FIRST(&proc->async_events);
3552 0 : STAILQ_REMOVE_HEAD(&proc->async_events, link);
3553 0 : spdk_free(event);
3554 : }
3555 :
3556 0 : TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
3557 0 : TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
3558 :
3559 : /*
3560 : * The process may have been killed while some qpairs were in their
3561 : * completion context. Clear that flag here to allow these IO
3562 : * qpairs to be deleted.
3563 : */
3564 0 : qpair->in_completion_context = 0;
3565 :
3566 0 : qpair->no_deletion_notification_needed = 1;
3567 :
3568 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
3569 : }
3570 :
3571 0 : spdk_free(proc);
3572 0 : }
3573 :
3574 : /**
3575 : * This function will be called when destructing the controller.
3576 : * 1. There is no more admin request on this controller.
3577 : * 2. Clean up any left resource allocation when its associated process is gone.
3578 : */
3579 : void
3580 50 : nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
3581 : {
3582 : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3583 :
3584 : /* Free all the processes' properties and make sure no pending admin IOs */
3585 53 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3586 3 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3587 :
3588 3 : assert(STAILQ_EMPTY(&active_proc->active_reqs));
3589 :
3590 3 : spdk_free(active_proc);
3591 : }
3592 50 : }
3593 :
3594 : /**
3595 : * This function will be called when any other process attaches or
3596 : * detaches the controller in order to cleanup those unexpectedly
3597 : * terminated processes.
3598 : * Note: the ctrlr_lock must be held when calling this function.
3599 : */
3600 : static int
3601 0 : nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
3602 : {
3603 : struct spdk_nvme_ctrlr_process *active_proc, *tmp;
3604 0 : int active_proc_count = 0;
3605 :
3606 0 : TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
3607 0 : if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
3608 0 : NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid);
3609 :
3610 0 : TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
3611 :
3612 0 : nvme_ctrlr_cleanup_process(active_proc);
3613 : } else {
3614 0 : active_proc_count++;
3615 : }
3616 : }
3617 :
3618 0 : return active_proc_count;
3619 : }
3620 :
3621 : void
3622 0 : nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
3623 : {
3624 : struct spdk_nvme_ctrlr_process *active_proc;
3625 :
3626 0 : nvme_ctrlr_lock(ctrlr);
3627 :
3628 0 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3629 :
3630 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3631 0 : if (active_proc) {
3632 0 : active_proc->ref++;
3633 : }
3634 :
3635 0 : nvme_ctrlr_unlock(ctrlr);
3636 0 : }
3637 :
3638 : void
3639 0 : nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
3640 : {
3641 : struct spdk_nvme_ctrlr_process *active_proc;
3642 : int proc_count;
3643 :
3644 0 : nvme_ctrlr_lock(ctrlr);
3645 :
3646 0 : proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
3647 :
3648 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3649 0 : if (active_proc) {
3650 0 : active_proc->ref--;
3651 0 : assert(active_proc->ref >= 0);
3652 :
3653 : /*
3654 : * The last active process will be removed at the end of
3655 : * the destruction of the controller.
3656 : */
3657 0 : if (active_proc->ref == 0 && proc_count != 1) {
3658 0 : nvme_ctrlr_remove_process(ctrlr, active_proc);
3659 : }
3660 : }
3661 :
3662 0 : nvme_ctrlr_unlock(ctrlr);
3663 0 : }
3664 :
3665 : int
3666 0 : nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
3667 : {
3668 : struct spdk_nvme_ctrlr_process *active_proc;
3669 0 : int ref = 0;
3670 :
3671 0 : nvme_ctrlr_lock(ctrlr);
3672 :
3673 0 : nvme_ctrlr_remove_inactive_proc(ctrlr);
3674 :
3675 0 : TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
3676 0 : ref += active_proc->ref;
3677 : }
3678 :
3679 0 : nvme_ctrlr_unlock(ctrlr);
3680 :
3681 0 : return ref;
3682 : }
3683 :
3684 : /**
3685 : * Get the PCI device handle which is only visible to its associated process.
3686 : */
3687 : struct spdk_pci_device *
3688 0 : nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
3689 : {
3690 : struct spdk_nvme_ctrlr_process *active_proc;
3691 0 : struct spdk_pci_device *devhandle = NULL;
3692 :
3693 0 : nvme_ctrlr_lock(ctrlr);
3694 :
3695 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
3696 0 : if (active_proc) {
3697 0 : devhandle = active_proc->devhandle;
3698 : }
3699 :
3700 0 : nvme_ctrlr_unlock(ctrlr);
3701 :
3702 0 : return devhandle;
3703 : }
3704 :
3705 : static void
3706 21 : nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3707 : {
3708 21 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3709 :
3710 21 : if (spdk_nvme_cpl_is_error(cpl)) {
3711 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n");
3712 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3713 0 : return;
3714 : }
3715 :
3716 21 : assert(value <= UINT32_MAX);
3717 21 : ctrlr->vs.raw = (uint32_t)value;
3718 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE);
3719 : }
3720 :
3721 : static void
3722 21 : nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3723 : {
3724 21 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3725 :
3726 21 : if (spdk_nvme_cpl_is_error(cpl)) {
3727 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n");
3728 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3729 0 : return;
3730 : }
3731 :
3732 21 : ctrlr->cap.raw = value;
3733 21 : nvme_ctrlr_init_cap(ctrlr);
3734 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE);
3735 : }
3736 :
3737 : static void
3738 22 : nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3739 : {
3740 22 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3741 : enum nvme_ctrlr_state state;
3742 :
3743 22 : if (spdk_nvme_cpl_is_error(cpl)) {
3744 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3745 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3746 0 : return;
3747 : }
3748 :
3749 22 : assert(value <= UINT32_MAX);
3750 22 : ctrlr->process_init_cc.raw = (uint32_t)value;
3751 :
3752 22 : if (ctrlr->process_init_cc.bits.en) {
3753 2 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n");
3754 2 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1;
3755 : } else {
3756 20 : state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0;
3757 : }
3758 :
3759 22 : nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr));
3760 : }
3761 :
3762 : static void
3763 2 : nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3764 : {
3765 2 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3766 :
3767 2 : if (spdk_nvme_cpl_is_error(cpl)) {
3768 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n");
3769 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3770 0 : return;
3771 : }
3772 :
3773 : /*
3774 : * Wait 2.5 seconds before accessing PCI registers.
3775 : * Not using sleep() to avoid blocking other controller's initialization.
3776 : */
3777 2 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
3778 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n");
3779 0 : ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000);
3780 : }
3781 :
3782 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3783 : nvme_ctrlr_get_ready_timeout(ctrlr));
3784 : }
3785 :
3786 : static void
3787 2 : nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3788 : {
3789 2 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3790 : union spdk_nvme_cc_register cc;
3791 : int rc;
3792 :
3793 2 : if (spdk_nvme_cpl_is_error(cpl)) {
3794 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n");
3795 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3796 0 : return;
3797 : }
3798 :
3799 2 : assert(value <= UINT32_MAX);
3800 2 : cc.raw = (uint32_t)value;
3801 2 : cc.bits.en = 0;
3802 2 : ctrlr->process_init_cc.raw = cc.raw;
3803 :
3804 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC,
3805 : nvme_ctrlr_get_ready_timeout(ctrlr));
3806 :
3807 2 : rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr);
3808 2 : if (rc != 0) {
3809 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n");
3810 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3811 : }
3812 : }
3813 :
3814 : static void
3815 2 : nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3816 : {
3817 2 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3818 : union spdk_nvme_csts_register csts;
3819 :
3820 2 : if (spdk_nvme_cpl_is_error(cpl)) {
3821 : /* While a device is resetting, it may be unable to service MMIO reads
3822 : * temporarily. Allow for this case.
3823 : */
3824 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3825 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
3826 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3827 : NVME_TIMEOUT_KEEP_EXISTING);
3828 : } else {
3829 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3830 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3831 : }
3832 :
3833 0 : return;
3834 : }
3835 :
3836 2 : assert(value <= UINT32_MAX);
3837 2 : csts.raw = (uint32_t)value;
3838 2 : if (csts.bits.rdy == 1 || csts.bits.cfs == 1) {
3839 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0,
3840 : nvme_ctrlr_get_ready_timeout(ctrlr));
3841 : } else {
3842 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
3843 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1,
3844 : NVME_TIMEOUT_KEEP_EXISTING);
3845 : }
3846 : }
3847 :
3848 : static void
3849 22 : nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl)
3850 : {
3851 22 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3852 : union spdk_nvme_csts_register csts;
3853 :
3854 22 : if (spdk_nvme_cpl_is_error(cpl)) {
3855 : /* While a device is resetting, it may be unable to service MMIO reads
3856 : * temporarily. Allow for this case.
3857 : */
3858 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3859 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
3860 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3861 : NVME_TIMEOUT_KEEP_EXISTING);
3862 : } else {
3863 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3864 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3865 : }
3866 :
3867 0 : return;
3868 : }
3869 :
3870 22 : assert(value <= UINT32_MAX);
3871 22 : csts.raw = (uint32_t)value;
3872 22 : if (csts.bits.rdy == 0) {
3873 22 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n");
3874 22 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED,
3875 : nvme_ctrlr_get_ready_timeout(ctrlr));
3876 : } else {
3877 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,
3878 : NVME_TIMEOUT_KEEP_EXISTING);
3879 : }
3880 : }
3881 :
3882 : static void
3883 9 : nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value,
3884 : const struct spdk_nvme_cpl *cpl)
3885 : {
3886 9 : struct spdk_nvme_ctrlr *ctrlr = ctx;
3887 : union spdk_nvme_csts_register csts;
3888 :
3889 9 : if (spdk_nvme_cpl_is_error(cpl)) {
3890 : /* While a device is resetting, it may be unable to service MMIO reads
3891 : * temporarily. Allow for this case.
3892 : */
3893 0 : if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3894 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n");
3895 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3896 : NVME_TIMEOUT_KEEP_EXISTING);
3897 : } else {
3898 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n");
3899 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3900 : }
3901 :
3902 0 : return;
3903 : }
3904 :
3905 9 : assert(value <= UINT32_MAX);
3906 9 : csts.raw = value;
3907 9 : if (csts.bits.rdy == 1) {
3908 9 : NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
3909 : /*
3910 : * The controller has been enabled.
3911 : * Perform the rest of initialization serially.
3912 : */
3913 9 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3914 9 : ctrlr->opts.admin_timeout_ms);
3915 : } else {
3916 0 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1,
3917 : NVME_TIMEOUT_KEEP_EXISTING);
3918 : }
3919 : }
3920 :
3921 : /**
3922 : * This function will be called repeatedly during initialization until the controller is ready.
3923 : */
3924 : int
3925 446 : nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
3926 : {
3927 : uint32_t ready_timeout_in_ms;
3928 : uint64_t ticks;
3929 446 : int rc = 0;
3930 :
3931 446 : ticks = spdk_get_ticks();
3932 :
3933 : /*
3934 : * May need to avoid accessing any register on the target controller
3935 : * for a while. Return early without touching the FSM.
3936 : * Check sleep_timeout_tsc > 0 for unit test.
3937 : */
3938 446 : if ((ctrlr->sleep_timeout_tsc > 0) &&
3939 2 : (ticks <= ctrlr->sleep_timeout_tsc)) {
3940 1 : return 0;
3941 : }
3942 445 : ctrlr->sleep_timeout_tsc = 0;
3943 :
3944 445 : ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr);
3945 :
3946 : /*
3947 : * Check if the current initialization step is done or has timed out.
3948 : */
3949 445 : switch (ctrlr->state) {
3950 1 : case NVME_CTRLR_STATE_INIT_DELAY:
3951 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3952 1 : if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
3953 : /*
3954 : * Controller may need some delay before it's enabled.
3955 : *
3956 : * This is a workaround for an issue where the PCIe-attached NVMe controller
3957 : * is not ready after VFIO reset. We delay the initialization rather than the
3958 : * enabling itself, because this is required only for the very first enabling
3959 : * - directly after a VFIO reset.
3960 : */
3961 1 : NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n");
3962 1 : ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
3963 : }
3964 1 : break;
3965 :
3966 0 : case NVME_CTRLR_STATE_DISCONNECTED:
3967 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3968 0 : break;
3969 :
3970 21 : case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */
3971 21 : rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
3972 21 : if (rc == 0) {
3973 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ,
3974 : NVME_TIMEOUT_INFINITE);
3975 : } else {
3976 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
3977 : }
3978 21 : break;
3979 :
3980 21 : case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ:
3981 21 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3982 :
3983 21 : switch (nvme_qpair_get_state(ctrlr->adminq)) {
3984 0 : case NVME_QPAIR_CONNECTING:
3985 0 : break;
3986 21 : case NVME_QPAIR_CONNECTED:
3987 21 : nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
3988 : /* Fall through */
3989 21 : case NVME_QPAIR_ENABLED:
3990 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS,
3991 : NVME_TIMEOUT_INFINITE);
3992 : /* Abort any queued requests that were sent while the adminq was connecting
3993 : * to avoid stalling the init process during a reset, as requests don't get
3994 : * resubmitted while the controller is resetting and subsequent commands
3995 : * would get queued too.
3996 : */
3997 21 : nvme_qpair_abort_queued_reqs(ctrlr->adminq);
3998 21 : break;
3999 0 : case NVME_QPAIR_DISCONNECTING:
4000 0 : assert(ctrlr->adminq->async == true);
4001 0 : break;
4002 0 : case NVME_QPAIR_DISCONNECTED:
4003 : /* fallthrough */
4004 : default:
4005 0 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4006 0 : break;
4007 : }
4008 :
4009 21 : break;
4010 :
4011 21 : case NVME_CTRLR_STATE_READ_VS:
4012 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE);
4013 21 : rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr);
4014 21 : break;
4015 :
4016 21 : case NVME_CTRLR_STATE_READ_CAP:
4017 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE);
4018 21 : rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr);
4019 21 : break;
4020 :
4021 22 : case NVME_CTRLR_STATE_CHECK_EN:
4022 : /* Begin the hardware initialization by making sure the controller is disabled. */
4023 22 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms);
4024 22 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr);
4025 22 : break;
4026 :
4027 2 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
4028 : /*
4029 : * Controller is currently enabled. We need to disable it to cause a reset.
4030 : *
4031 : * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
4032 : * Wait for the ready bit to be 1 before disabling the controller.
4033 : */
4034 2 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
4035 : NVME_TIMEOUT_KEEP_EXISTING);
4036 2 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr);
4037 2 : break;
4038 :
4039 2 : case NVME_CTRLR_STATE_SET_EN_0:
4040 2 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n");
4041 2 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms);
4042 2 : rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr);
4043 2 : break;
4044 :
4045 22 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
4046 22 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS,
4047 : NVME_TIMEOUT_KEEP_EXISTING);
4048 22 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr);
4049 22 : break;
4050 :
4051 21 : case NVME_CTRLR_STATE_DISABLED:
4052 21 : if (ctrlr->is_disconnecting) {
4053 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n");
4054 : } else {
4055 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
4056 :
4057 : /*
4058 : * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting
4059 : * set to 1 if it is too soon after CSTS.RDY is reported as 0.
4060 : */
4061 21 : spdk_delay_us(100);
4062 : }
4063 21 : break;
4064 :
4065 21 : case NVME_CTRLR_STATE_ENABLE:
4066 21 : NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n");
4067 21 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms);
4068 21 : rc = nvme_ctrlr_enable(ctrlr);
4069 21 : if (rc) {
4070 7 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc);
4071 : }
4072 21 : return rc;
4073 :
4074 9 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
4075 9 : nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS,
4076 : NVME_TIMEOUT_KEEP_EXISTING);
4077 9 : rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1,
4078 : ctrlr);
4079 9 : break;
4080 :
4081 9 : case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
4082 9 : nvme_transport_qpair_reset(ctrlr->adminq);
4083 9 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE);
4084 9 : break;
4085 :
4086 16 : case NVME_CTRLR_STATE_IDENTIFY:
4087 16 : rc = nvme_ctrlr_identify(ctrlr);
4088 16 : break;
4089 :
4090 19 : case NVME_CTRLR_STATE_CONFIGURE_AER:
4091 19 : rc = nvme_ctrlr_configure_aer(ctrlr);
4092 19 : break;
4093 :
4094 22 : case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
4095 22 : rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
4096 22 : break;
4097 :
4098 19 : case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
4099 19 : rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
4100 19 : break;
4101 :
4102 0 : case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
4103 0 : rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
4104 0 : break;
4105 :
4106 19 : case NVME_CTRLR_STATE_SET_NUM_QUEUES:
4107 19 : nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
4108 19 : rc = nvme_ctrlr_set_num_queues(ctrlr);
4109 19 : break;
4110 :
4111 24 : case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
4112 24 : _nvme_ctrlr_identify_active_ns(ctrlr);
4113 24 : break;
4114 :
4115 14 : case NVME_CTRLR_STATE_IDENTIFY_NS:
4116 14 : rc = nvme_ctrlr_identify_namespaces(ctrlr);
4117 14 : break;
4118 :
4119 14 : case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
4120 14 : rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
4121 14 : break;
4122 :
4123 14 : case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
4124 14 : rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
4125 14 : break;
4126 :
4127 15 : case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
4128 15 : rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
4129 15 : break;
4130 :
4131 1 : case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES:
4132 1 : rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
4133 1 : break;
4134 :
4135 14 : case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
4136 14 : nvme_ctrlr_set_supported_features(ctrlr);
4137 14 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_FEATURE,
4138 14 : ctrlr->opts.admin_timeout_ms);
4139 14 : break;
4140 :
4141 16 : case NVME_CTRLR_STATE_SET_HOST_FEATURE:
4142 16 : rc = nvme_ctrlr_set_host_feature(ctrlr);
4143 16 : break;
4144 :
4145 14 : case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
4146 14 : rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
4147 14 : break;
4148 :
4149 14 : case NVME_CTRLR_STATE_SET_HOST_ID:
4150 14 : rc = nvme_ctrlr_set_host_id(ctrlr);
4151 14 : break;
4152 :
4153 17 : case NVME_CTRLR_STATE_TRANSPORT_READY:
4154 17 : rc = nvme_transport_ctrlr_ready(ctrlr);
4155 17 : if (rc) {
4156 1 : NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc);
4157 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
4158 : } else {
4159 16 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
4160 : }
4161 17 : break;
4162 :
4163 0 : case NVME_CTRLR_STATE_READY:
4164 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n");
4165 0 : return 0;
4166 :
4167 0 : case NVME_CTRLR_STATE_ERROR:
4168 0 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n");
4169 0 : return -1;
4170 :
4171 0 : case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS:
4172 : case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP:
4173 : case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC:
4174 : case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC:
4175 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4176 : case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS:
4177 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC:
4178 : case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS:
4179 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
4180 : case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
4181 : case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
4182 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
4183 : case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
4184 : case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
4185 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
4186 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
4187 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
4188 : case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
4189 : case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES:
4190 : case NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE:
4191 : case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
4192 : case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
4193 : /*
4194 : * nvme_ctrlr_process_init() may be called from the completion context
4195 : * for the admin qpair. Avoid recursive calls for this case.
4196 : */
4197 0 : if (!ctrlr->adminq->in_completion_context) {
4198 0 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4199 : }
4200 0 : break;
4201 :
4202 0 : default:
4203 0 : assert(0);
4204 : return -1;
4205 : }
4206 :
4207 424 : if (rc) {
4208 1 : NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n",
4209 : rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4210 : }
4211 :
4212 : /* Note: we use the ticks captured when we entered this function.
4213 : * This covers environments where the SPDK process gets swapped out after
4214 : * we tried to advance the state but before we check the timeout here.
4215 : * It is not normal for this to happen, but harmless to handle it in this
4216 : * way.
4217 : */
4218 424 : if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
4219 0 : ticks > ctrlr->state_timeout_tsc) {
4220 0 : NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n",
4221 : ctrlr->state, nvme_ctrlr_state_string(ctrlr->state));
4222 0 : return -1;
4223 : }
4224 :
4225 424 : return rc;
4226 : }
4227 :
4228 : int
4229 47 : nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
4230 : {
4231 47 : pthread_mutexattr_t attr;
4232 47 : int rc = 0;
4233 :
4234 47 : if (pthread_mutexattr_init(&attr)) {
4235 0 : return -1;
4236 : }
4237 94 : if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
4238 : #ifndef __FreeBSD__
4239 94 : pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
4240 94 : pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
4241 : #endif
4242 47 : pthread_mutex_init(mtx, &attr)) {
4243 0 : rc = -1;
4244 : }
4245 47 : pthread_mutexattr_destroy(&attr);
4246 47 : return rc;
4247 : }
4248 :
4249 : int
4250 47 : nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
4251 : {
4252 : int rc;
4253 :
4254 47 : if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
4255 1 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
4256 : } else {
4257 46 : nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
4258 : }
4259 :
4260 47 : if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
4261 0 : NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
4262 : ctrlr->opts.admin_queue_size);
4263 0 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
4264 : }
4265 :
4266 47 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE &&
4267 0 : (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) {
4268 0 : NVME_CTRLR_ERRLOG(ctrlr,
4269 : "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n",
4270 : ctrlr->opts.admin_queue_size);
4271 0 : ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size,
4272 : SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE);
4273 : }
4274 :
4275 47 : if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
4276 26 : NVME_CTRLR_ERRLOG(ctrlr,
4277 : "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
4278 : ctrlr->opts.admin_queue_size);
4279 26 : ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
4280 : }
4281 :
4282 47 : ctrlr->flags = 0;
4283 47 : ctrlr->free_io_qids = NULL;
4284 47 : ctrlr->is_resetting = false;
4285 47 : ctrlr->is_failed = false;
4286 47 : ctrlr->is_destructed = false;
4287 :
4288 47 : TAILQ_INIT(&ctrlr->active_io_qpairs);
4289 47 : STAILQ_INIT(&ctrlr->queued_aborts);
4290 47 : ctrlr->outstanding_aborts = 0;
4291 :
4292 47 : ctrlr->ana_log_page = NULL;
4293 47 : ctrlr->ana_log_page_size = 0;
4294 :
4295 47 : rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
4296 47 : if (rc != 0) {
4297 0 : return rc;
4298 : }
4299 :
4300 47 : TAILQ_INIT(&ctrlr->active_procs);
4301 47 : STAILQ_INIT(&ctrlr->register_operations);
4302 :
4303 47 : RB_INIT(&ctrlr->ns);
4304 :
4305 47 : return rc;
4306 : }
4307 :
4308 : static void
4309 21 : nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr)
4310 : {
4311 21 : if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
4312 5 : ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
4313 : }
4314 :
4315 21 : ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
4316 :
4317 : /* For now, always select page_size == min_page_size. */
4318 21 : ctrlr->page_size = ctrlr->min_page_size;
4319 :
4320 21 : ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
4321 21 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
4322 21 : if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE &&
4323 0 : ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) {
4324 : /* If the user specifically set an IO queue size different than the
4325 : * default, use that value. Otherwise overwrite with the quirked value.
4326 : * This allows this quirk to be overridden when necessary.
4327 : * However, cap.mqes still needs to be respected.
4328 : */
4329 0 : ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK;
4330 : }
4331 21 : ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
4332 :
4333 21 : ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
4334 21 : }
4335 :
4336 : void
4337 47 : nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
4338 : {
4339 : int rc;
4340 :
4341 47 : if (ctrlr->lock_depth > 0) {
4342 0 : SPDK_ERRLOG("lock currently held (depth=%d)!\n", ctrlr->lock_depth);
4343 0 : assert(false);
4344 : }
4345 :
4346 47 : rc = pthread_mutex_destroy(&ctrlr->ctrlr_lock);
4347 47 : if (rc) {
4348 0 : SPDK_ERRLOG("could not destroy ctrlr_lock: %s\n", spdk_strerror(rc));
4349 0 : assert(false);
4350 : }
4351 :
4352 47 : nvme_ctrlr_free_processes(ctrlr);
4353 47 : }
4354 :
4355 : void
4356 47 : nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
4357 : struct nvme_ctrlr_detach_ctx *ctx)
4358 : {
4359 : struct spdk_nvme_qpair *qpair, *tmp;
4360 :
4361 47 : NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n");
4362 :
4363 47 : ctrlr->prepare_for_reset = false;
4364 47 : ctrlr->is_destructed = true;
4365 :
4366 47 : spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4367 :
4368 47 : nvme_ctrlr_abort_queued_aborts(ctrlr);
4369 47 : nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
4370 :
4371 47 : TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
4372 0 : spdk_nvme_ctrlr_free_io_qpair(qpair);
4373 : }
4374 :
4375 47 : nvme_ctrlr_free_doorbell_buffer(ctrlr);
4376 47 : nvme_ctrlr_free_iocs_specific_data(ctrlr);
4377 :
4378 47 : nvme_ctrlr_shutdown_async(ctrlr, ctx);
4379 47 : }
4380 :
4381 : int
4382 86 : nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
4383 : struct nvme_ctrlr_detach_ctx *ctx)
4384 : {
4385 : struct spdk_nvme_ns *ns, *tmp_ns;
4386 86 : int rc = 0;
4387 :
4388 86 : if (!ctx->shutdown_complete) {
4389 78 : rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
4390 78 : if (rc == -EAGAIN) {
4391 39 : return -EAGAIN;
4392 : }
4393 : /* Destruct ctrlr forcefully for any other error. */
4394 : }
4395 :
4396 47 : if (ctx->cb_fn) {
4397 0 : ctx->cb_fn(ctrlr);
4398 : }
4399 :
4400 47 : nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
4401 :
4402 7733 : RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) {
4403 7686 : nvme_ctrlr_destruct_namespace(ctrlr, ns->id);
4404 7686 : RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns);
4405 7686 : spdk_free(ns);
4406 : }
4407 :
4408 47 : ctrlr->active_ns_count = 0;
4409 :
4410 47 : spdk_bit_array_free(&ctrlr->free_io_qids);
4411 :
4412 47 : free(ctrlr->ana_log_page);
4413 47 : free(ctrlr->copied_ana_desc);
4414 47 : ctrlr->ana_log_page = NULL;
4415 47 : ctrlr->copied_ana_desc = NULL;
4416 47 : ctrlr->ana_log_page_size = 0;
4417 :
4418 47 : nvme_transport_ctrlr_destruct(ctrlr);
4419 :
4420 47 : return rc;
4421 : }
4422 :
4423 : void
4424 47 : nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
4425 : {
4426 47 : struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr };
4427 : int rc;
4428 :
4429 47 : nvme_ctrlr_destruct_async(ctrlr, &ctx);
4430 :
4431 : while (1) {
4432 86 : rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
4433 86 : if (rc != -EAGAIN) {
4434 47 : break;
4435 : }
4436 39 : nvme_delay(1000);
4437 : }
4438 47 : }
4439 :
4440 : int
4441 24 : nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
4442 : struct nvme_request *req)
4443 : {
4444 24 : return nvme_qpair_submit_request(ctrlr->adminq, req);
4445 : }
4446 :
4447 : static void
4448 0 : nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
4449 : {
4450 : /* Do nothing */
4451 0 : }
4452 :
4453 : /*
4454 : * Check if we need to send a Keep Alive command.
4455 : * Caller must hold ctrlr->ctrlr_lock.
4456 : */
4457 : static int
4458 0 : nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
4459 : {
4460 : uint64_t now;
4461 : struct nvme_request *req;
4462 : struct spdk_nvme_cmd *cmd;
4463 0 : int rc = 0;
4464 :
4465 0 : now = spdk_get_ticks();
4466 0 : if (now < ctrlr->next_keep_alive_tick) {
4467 0 : return rc;
4468 : }
4469 :
4470 0 : req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
4471 0 : if (req == NULL) {
4472 0 : return rc;
4473 : }
4474 :
4475 0 : cmd = &req->cmd;
4476 0 : cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
4477 :
4478 0 : rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
4479 0 : if (rc != 0) {
4480 0 : NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n");
4481 0 : rc = -ENXIO;
4482 : }
4483 :
4484 0 : ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
4485 0 : return rc;
4486 : }
4487 :
4488 : int32_t
4489 1 : spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
4490 : {
4491 : int32_t num_completions;
4492 : int32_t rc;
4493 : struct spdk_nvme_ctrlr_process *active_proc;
4494 :
4495 1 : nvme_ctrlr_lock(ctrlr);
4496 :
4497 1 : if (ctrlr->keep_alive_interval_ticks) {
4498 0 : rc = nvme_ctrlr_keep_alive(ctrlr);
4499 0 : if (rc) {
4500 0 : nvme_ctrlr_unlock(ctrlr);
4501 0 : return rc;
4502 : }
4503 : }
4504 :
4505 1 : rc = nvme_io_msg_process(ctrlr);
4506 1 : if (rc < 0) {
4507 0 : nvme_ctrlr_unlock(ctrlr);
4508 0 : return rc;
4509 : }
4510 1 : num_completions = rc;
4511 :
4512 1 : rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
4513 :
4514 : /* Each process has an async list, complete the ones for this process object */
4515 1 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4516 1 : if (active_proc) {
4517 0 : nvme_ctrlr_complete_queued_async_events(ctrlr);
4518 : }
4519 :
4520 1 : if (rc == -ENXIO && ctrlr->is_disconnecting) {
4521 1 : nvme_ctrlr_disconnect_done(ctrlr);
4522 : }
4523 :
4524 1 : nvme_ctrlr_unlock(ctrlr);
4525 :
4526 1 : if (rc < 0) {
4527 1 : num_completions = rc;
4528 : } else {
4529 0 : num_completions += rc;
4530 : }
4531 :
4532 1 : return num_completions;
4533 : }
4534 :
4535 : const struct spdk_nvme_ctrlr_data *
4536 0 : spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
4537 : {
4538 0 : return &ctrlr->cdata;
4539 : }
4540 :
4541 0 : union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
4542 : {
4543 0 : union spdk_nvme_csts_register csts;
4544 :
4545 0 : if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
4546 0 : csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4547 : }
4548 0 : return csts;
4549 : }
4550 :
4551 0 : union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr)
4552 : {
4553 0 : union spdk_nvme_cc_register cc;
4554 :
4555 0 : if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
4556 0 : cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
4557 : }
4558 0 : return cc;
4559 : }
4560 :
4561 0 : union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
4562 : {
4563 0 : return ctrlr->cap;
4564 : }
4565 :
4566 0 : union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
4567 : {
4568 0 : return ctrlr->vs;
4569 : }
4570 :
4571 0 : union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
4572 : {
4573 0 : union spdk_nvme_cmbsz_register cmbsz;
4574 :
4575 0 : if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
4576 0 : cmbsz.raw = 0;
4577 : }
4578 :
4579 0 : return cmbsz;
4580 : }
4581 :
4582 0 : union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr)
4583 : {
4584 0 : union spdk_nvme_pmrcap_register pmrcap;
4585 :
4586 0 : if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) {
4587 0 : pmrcap.raw = 0;
4588 : }
4589 :
4590 0 : return pmrcap;
4591 : }
4592 :
4593 0 : union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr)
4594 : {
4595 0 : union spdk_nvme_bpinfo_register bpinfo;
4596 :
4597 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
4598 0 : bpinfo.raw = 0;
4599 : }
4600 :
4601 0 : return bpinfo;
4602 : }
4603 :
4604 : uint64_t
4605 0 : spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr)
4606 : {
4607 0 : return ctrlr->pmr_size;
4608 : }
4609 :
4610 : uint32_t
4611 2 : spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
4612 : {
4613 2 : return ctrlr->cdata.nn;
4614 : }
4615 :
4616 : bool
4617 9301 : spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4618 : {
4619 9301 : struct spdk_nvme_ns tmp, *ns;
4620 :
4621 9301 : tmp.id = nsid;
4622 9301 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4623 :
4624 9301 : if (ns != NULL) {
4625 9209 : return ns->active;
4626 : }
4627 :
4628 92 : return false;
4629 : }
4630 :
4631 : uint32_t
4632 35 : spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
4633 : {
4634 : struct spdk_nvme_ns *ns;
4635 :
4636 35 : ns = RB_MIN(nvme_ns_tree, &ctrlr->ns);
4637 35 : if (ns == NULL) {
4638 10 : return 0;
4639 : }
4640 :
4641 4618 : while (ns != NULL) {
4642 4615 : if (ns->active) {
4643 22 : return ns->id;
4644 : }
4645 :
4646 4593 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4647 : }
4648 :
4649 3 : return 0;
4650 : }
4651 :
4652 : uint32_t
4653 4657 : spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
4654 : {
4655 4657 : struct spdk_nvme_ns tmp, *ns;
4656 :
4657 4657 : tmp.id = prev_nsid;
4658 4657 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4659 4657 : if (ns == NULL) {
4660 5 : return 0;
4661 : }
4662 :
4663 4652 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4664 6184 : while (ns != NULL) {
4665 6164 : if (ns->active) {
4666 4632 : return ns->id;
4667 : }
4668 :
4669 1532 : ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns);
4670 : }
4671 :
4672 20 : return 0;
4673 : }
4674 :
4675 : struct spdk_nvme_ns *
4676 12403 : spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4677 : {
4678 12403 : struct spdk_nvme_ns tmp;
4679 : struct spdk_nvme_ns *ns;
4680 :
4681 12403 : if (nsid < 1 || nsid > ctrlr->cdata.nn) {
4682 18 : return NULL;
4683 : }
4684 :
4685 12385 : nvme_ctrlr_lock(ctrlr);
4686 :
4687 12385 : tmp.id = nsid;
4688 12385 : ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp);
4689 :
4690 12385 : if (ns == NULL) {
4691 7687 : ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
4692 7687 : if (ns == NULL) {
4693 0 : nvme_ctrlr_unlock(ctrlr);
4694 0 : return NULL;
4695 : }
4696 :
4697 7687 : NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid);
4698 7687 : ns->id = nsid;
4699 7687 : RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns);
4700 : }
4701 :
4702 12385 : nvme_ctrlr_unlock(ctrlr);
4703 :
4704 12385 : return ns;
4705 : }
4706 :
4707 : struct spdk_pci_device *
4708 0 : spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
4709 : {
4710 0 : if (ctrlr == NULL) {
4711 0 : return NULL;
4712 : }
4713 :
4714 0 : if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
4715 0 : return NULL;
4716 : }
4717 :
4718 0 : return nvme_ctrlr_proc_get_devhandle(ctrlr);
4719 : }
4720 :
4721 : uint32_t
4722 0 : spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
4723 : {
4724 0 : return ctrlr->max_xfer_size;
4725 : }
4726 :
4727 : uint16_t
4728 0 : spdk_nvme_ctrlr_get_max_sges(const struct spdk_nvme_ctrlr *ctrlr)
4729 : {
4730 0 : if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) {
4731 0 : return ctrlr->max_sges;
4732 : } else {
4733 0 : return UINT16_MAX;
4734 : }
4735 : }
4736 :
4737 : void
4738 2 : spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
4739 : spdk_nvme_aer_cb aer_cb_fn,
4740 : void *aer_cb_arg)
4741 : {
4742 : struct spdk_nvme_ctrlr_process *active_proc;
4743 :
4744 2 : nvme_ctrlr_lock(ctrlr);
4745 :
4746 2 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4747 2 : if (active_proc) {
4748 2 : active_proc->aer_cb_fn = aer_cb_fn;
4749 2 : active_proc->aer_cb_arg = aer_cb_arg;
4750 : }
4751 :
4752 2 : nvme_ctrlr_unlock(ctrlr);
4753 2 : }
4754 :
4755 : void
4756 0 : spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr)
4757 : {
4758 0 : ctrlr->opts.disable_read_changed_ns_list_log_page = true;
4759 0 : }
4760 :
4761 : void
4762 0 : spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
4763 : uint64_t timeout_io_us, uint64_t timeout_admin_us,
4764 : spdk_nvme_timeout_cb cb_fn, void *cb_arg)
4765 : {
4766 : struct spdk_nvme_ctrlr_process *active_proc;
4767 :
4768 0 : nvme_ctrlr_lock(ctrlr);
4769 :
4770 0 : active_proc = nvme_ctrlr_get_current_process(ctrlr);
4771 0 : if (active_proc) {
4772 0 : active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL;
4773 0 : active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL;
4774 0 : active_proc->timeout_cb_fn = cb_fn;
4775 0 : active_proc->timeout_cb_arg = cb_arg;
4776 : }
4777 :
4778 0 : ctrlr->timeout_enabled = true;
4779 :
4780 0 : nvme_ctrlr_unlock(ctrlr);
4781 0 : }
4782 :
4783 : bool
4784 8 : spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
4785 : {
4786 : /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
4787 : SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
4788 8 : return ctrlr->log_page_supported[log_page];
4789 : }
4790 :
4791 : bool
4792 4 : spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
4793 : {
4794 : /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
4795 : SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
4796 4 : return ctrlr->feature_supported[feature_code];
4797 : }
4798 :
4799 : int
4800 1 : spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4801 : struct spdk_nvme_ctrlr_list *payload)
4802 : {
4803 : struct nvme_completion_poll_status *status;
4804 : struct spdk_nvme_ns *ns;
4805 : int res;
4806 :
4807 1 : if (nsid == 0) {
4808 0 : return -EINVAL;
4809 : }
4810 :
4811 1 : status = calloc(1, sizeof(*status));
4812 1 : if (!status) {
4813 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4814 0 : return -ENOMEM;
4815 : }
4816 :
4817 1 : res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
4818 : nvme_completion_poll_cb, status);
4819 1 : if (res) {
4820 0 : free(status);
4821 0 : return res;
4822 : }
4823 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4824 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n");
4825 0 : if (!status->timed_out) {
4826 0 : free(status);
4827 : }
4828 0 : return -ENXIO;
4829 : }
4830 1 : free(status);
4831 :
4832 1 : res = nvme_ctrlr_identify_active_ns(ctrlr);
4833 1 : if (res) {
4834 0 : return res;
4835 : }
4836 :
4837 1 : ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
4838 1 : if (ns == NULL) {
4839 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n");
4840 0 : return -ENXIO;
4841 : }
4842 :
4843 1 : return nvme_ns_construct(ns, nsid, ctrlr);
4844 : }
4845 :
4846 : int
4847 1 : spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4848 : struct spdk_nvme_ctrlr_list *payload)
4849 : {
4850 : struct nvme_completion_poll_status *status;
4851 : int res;
4852 :
4853 1 : if (nsid == 0) {
4854 0 : return -EINVAL;
4855 : }
4856 :
4857 1 : status = calloc(1, sizeof(*status));
4858 1 : if (!status) {
4859 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4860 0 : return -ENOMEM;
4861 : }
4862 :
4863 1 : res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
4864 : nvme_completion_poll_cb, status);
4865 1 : if (res) {
4866 0 : free(status);
4867 0 : return res;
4868 : }
4869 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4870 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n");
4871 0 : if (!status->timed_out) {
4872 0 : free(status);
4873 : }
4874 0 : return -ENXIO;
4875 : }
4876 1 : free(status);
4877 :
4878 1 : return nvme_ctrlr_identify_active_ns(ctrlr);
4879 : }
4880 :
4881 : uint32_t
4882 1 : spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
4883 : {
4884 : struct nvme_completion_poll_status *status;
4885 : int res;
4886 : uint32_t nsid;
4887 :
4888 1 : status = calloc(1, sizeof(*status));
4889 1 : if (!status) {
4890 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4891 0 : return 0;
4892 : }
4893 :
4894 1 : res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
4895 1 : if (res) {
4896 0 : free(status);
4897 0 : return 0;
4898 : }
4899 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4900 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n");
4901 0 : if (!status->timed_out) {
4902 0 : free(status);
4903 : }
4904 0 : return 0;
4905 : }
4906 :
4907 1 : nsid = status->cpl.cdw0;
4908 1 : free(status);
4909 :
4910 1 : assert(nsid > 0);
4911 :
4912 : /* Return the namespace ID that was created */
4913 1 : return nsid;
4914 : }
4915 :
4916 : int
4917 1 : spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
4918 : {
4919 : struct nvme_completion_poll_status *status;
4920 : int res;
4921 :
4922 1 : if (nsid == 0) {
4923 0 : return -EINVAL;
4924 : }
4925 :
4926 1 : status = calloc(1, sizeof(*status));
4927 1 : if (!status) {
4928 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4929 0 : return -ENOMEM;
4930 : }
4931 :
4932 1 : res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
4933 1 : if (res) {
4934 0 : free(status);
4935 0 : return res;
4936 : }
4937 1 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4938 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n");
4939 0 : if (!status->timed_out) {
4940 0 : free(status);
4941 : }
4942 0 : return -ENXIO;
4943 : }
4944 1 : free(status);
4945 :
4946 1 : return nvme_ctrlr_identify_active_ns(ctrlr);
4947 : }
4948 :
4949 : int
4950 0 : spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
4951 : struct spdk_nvme_format *format)
4952 : {
4953 : struct nvme_completion_poll_status *status;
4954 : int res;
4955 :
4956 0 : status = calloc(1, sizeof(*status));
4957 0 : if (!status) {
4958 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
4959 0 : return -ENOMEM;
4960 : }
4961 :
4962 0 : res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
4963 : status);
4964 0 : if (res) {
4965 0 : free(status);
4966 0 : return res;
4967 : }
4968 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4969 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n");
4970 0 : if (!status->timed_out) {
4971 0 : free(status);
4972 : }
4973 0 : return -ENXIO;
4974 : }
4975 0 : free(status);
4976 :
4977 0 : return spdk_nvme_ctrlr_reset(ctrlr);
4978 : }
4979 :
4980 : int
4981 8 : spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
4982 : int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
4983 : {
4984 8 : struct spdk_nvme_fw_commit fw_commit;
4985 : struct nvme_completion_poll_status *status;
4986 : int res;
4987 : unsigned int size_remaining;
4988 : unsigned int offset;
4989 : unsigned int transfer;
4990 : uint8_t *p;
4991 :
4992 8 : if (!completion_status) {
4993 0 : return -EINVAL;
4994 : }
4995 8 : memset(completion_status, 0, sizeof(struct spdk_nvme_status));
4996 8 : if (size % 4) {
4997 1 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n");
4998 1 : return -1;
4999 : }
5000 :
5001 : /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
5002 : * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
5003 : */
5004 7 : if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
5005 : (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
5006 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n");
5007 0 : return -1;
5008 : }
5009 :
5010 7 : status = calloc(1, sizeof(*status));
5011 7 : if (!status) {
5012 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5013 0 : return -ENOMEM;
5014 : }
5015 :
5016 : /* Firmware download */
5017 7 : size_remaining = size;
5018 7 : offset = 0;
5019 7 : p = payload;
5020 :
5021 10 : while (size_remaining > 0) {
5022 7 : transfer = spdk_min(size_remaining, ctrlr->min_page_size);
5023 :
5024 7 : memset(status, 0, sizeof(*status));
5025 7 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
5026 : nvme_completion_poll_cb,
5027 : status);
5028 7 : if (res) {
5029 2 : free(status);
5030 2 : return res;
5031 : }
5032 :
5033 5 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5034 2 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n");
5035 2 : if (!status->timed_out) {
5036 1 : free(status);
5037 : }
5038 2 : return -ENXIO;
5039 : }
5040 3 : p += transfer;
5041 3 : offset += transfer;
5042 3 : size_remaining -= transfer;
5043 : }
5044 :
5045 : /* Firmware commit */
5046 3 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5047 3 : fw_commit.fs = slot;
5048 3 : fw_commit.ca = commit_action;
5049 :
5050 3 : memset(status, 0, sizeof(*status));
5051 3 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
5052 : status);
5053 3 : if (res) {
5054 1 : free(status);
5055 1 : return res;
5056 : }
5057 :
5058 2 : res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
5059 :
5060 2 : memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
5061 :
5062 2 : if (!status->timed_out) {
5063 2 : free(status);
5064 : }
5065 :
5066 2 : if (res) {
5067 1 : if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
5068 0 : completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
5069 1 : if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
5070 0 : completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
5071 0 : NVME_CTRLR_NOTICELOG(ctrlr,
5072 : "firmware activation requires conventional reset to be performed. !\n");
5073 : } else {
5074 1 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5075 : }
5076 1 : return -ENXIO;
5077 : }
5078 : }
5079 :
5080 1 : return spdk_nvme_ctrlr_reset(ctrlr);
5081 : }
5082 :
5083 : int
5084 0 : spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
5085 : {
5086 : int rc, size;
5087 : union spdk_nvme_cmbsz_register cmbsz;
5088 :
5089 0 : cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
5090 :
5091 0 : if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
5092 0 : return -ENOTSUP;
5093 : }
5094 :
5095 0 : size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
5096 :
5097 0 : nvme_ctrlr_lock(ctrlr);
5098 0 : rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
5099 0 : nvme_ctrlr_unlock(ctrlr);
5100 :
5101 0 : if (rc < 0) {
5102 0 : return rc;
5103 : }
5104 :
5105 0 : return size;
5106 : }
5107 :
5108 : void *
5109 0 : spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5110 : {
5111 : void *buf;
5112 :
5113 0 : nvme_ctrlr_lock(ctrlr);
5114 0 : buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
5115 0 : nvme_ctrlr_unlock(ctrlr);
5116 :
5117 0 : return buf;
5118 : }
5119 :
5120 : void
5121 0 : spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
5122 : {
5123 0 : nvme_ctrlr_lock(ctrlr);
5124 0 : nvme_transport_ctrlr_unmap_cmb(ctrlr);
5125 0 : nvme_ctrlr_unlock(ctrlr);
5126 0 : }
5127 :
5128 : int
5129 0 : spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5130 : {
5131 : int rc;
5132 :
5133 0 : nvme_ctrlr_lock(ctrlr);
5134 0 : rc = nvme_transport_ctrlr_enable_pmr(ctrlr);
5135 0 : nvme_ctrlr_unlock(ctrlr);
5136 :
5137 0 : return rc;
5138 : }
5139 :
5140 : int
5141 0 : spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr)
5142 : {
5143 : int rc;
5144 :
5145 0 : nvme_ctrlr_lock(ctrlr);
5146 0 : rc = nvme_transport_ctrlr_disable_pmr(ctrlr);
5147 0 : nvme_ctrlr_unlock(ctrlr);
5148 :
5149 0 : return rc;
5150 : }
5151 :
5152 : void *
5153 0 : spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
5154 : {
5155 : void *buf;
5156 :
5157 0 : nvme_ctrlr_lock(ctrlr);
5158 0 : buf = nvme_transport_ctrlr_map_pmr(ctrlr, size);
5159 0 : nvme_ctrlr_unlock(ctrlr);
5160 :
5161 0 : return buf;
5162 : }
5163 :
5164 : int
5165 0 : spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr)
5166 : {
5167 : int rc;
5168 :
5169 0 : nvme_ctrlr_lock(ctrlr);
5170 0 : rc = nvme_transport_ctrlr_unmap_pmr(ctrlr);
5171 0 : nvme_ctrlr_unlock(ctrlr);
5172 :
5173 0 : return rc;
5174 : }
5175 :
5176 : int
5177 0 : spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload,
5178 : uint32_t bprsz, uint32_t bprof, uint32_t bpid)
5179 : {
5180 0 : union spdk_nvme_bprsel_register bprsel;
5181 0 : union spdk_nvme_bpinfo_register bpinfo;
5182 0 : uint64_t bpmbl, bpmb_size;
5183 :
5184 0 : if (ctrlr->cap.bits.bps == 0) {
5185 0 : return -ENOTSUP;
5186 : }
5187 :
5188 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5189 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5190 0 : return -EIO;
5191 : }
5192 :
5193 0 : if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) {
5194 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n");
5195 0 : return -EALREADY;
5196 : }
5197 :
5198 0 : nvme_ctrlr_lock(ctrlr);
5199 :
5200 0 : bpmb_size = bprsz * 4096;
5201 0 : bpmbl = spdk_vtophys(payload, &bpmb_size);
5202 0 : if (bpmbl == SPDK_VTOPHYS_ERROR) {
5203 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n");
5204 0 : nvme_ctrlr_unlock(ctrlr);
5205 0 : return -EFAULT;
5206 : }
5207 :
5208 0 : if (bpmb_size != bprsz * 4096) {
5209 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n");
5210 0 : nvme_ctrlr_unlock(ctrlr);
5211 0 : return -EFAULT;
5212 : }
5213 :
5214 0 : if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) {
5215 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n");
5216 0 : nvme_ctrlr_unlock(ctrlr);
5217 0 : return -EIO;
5218 : }
5219 :
5220 0 : bprsel.bits.bpid = bpid;
5221 0 : bprsel.bits.bprof = bprof;
5222 0 : bprsel.bits.bprsz = bprsz;
5223 :
5224 0 : if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) {
5225 0 : NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n");
5226 0 : nvme_ctrlr_unlock(ctrlr);
5227 0 : return -EIO;
5228 : }
5229 :
5230 0 : nvme_ctrlr_unlock(ctrlr);
5231 0 : return 0;
5232 : }
5233 :
5234 : int
5235 0 : spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr)
5236 : {
5237 0 : int rc = 0;
5238 0 : union spdk_nvme_bpinfo_register bpinfo;
5239 :
5240 0 : if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) {
5241 0 : NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n");
5242 0 : return -EIO;
5243 : }
5244 :
5245 0 : switch (bpinfo.bits.brs) {
5246 0 : case SPDK_NVME_BRS_NO_READ:
5247 0 : NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n");
5248 0 : rc = -EINVAL;
5249 0 : break;
5250 0 : case SPDK_NVME_BRS_READ_IN_PROGRESS:
5251 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n");
5252 0 : rc = -EAGAIN;
5253 0 : break;
5254 0 : case SPDK_NVME_BRS_READ_ERROR:
5255 0 : NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n");
5256 0 : rc = -EIO;
5257 0 : break;
5258 0 : case SPDK_NVME_BRS_READ_SUCCESS:
5259 0 : NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n");
5260 0 : break;
5261 0 : default:
5262 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n");
5263 0 : rc = -EINVAL;
5264 : }
5265 :
5266 0 : return rc;
5267 : }
5268 :
5269 : static void
5270 0 : nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl)
5271 : {
5272 : int res;
5273 0 : struct spdk_nvme_ctrlr *ctrlr = arg;
5274 0 : struct spdk_nvme_fw_commit fw_commit;
5275 0 : struct spdk_nvme_cpl err_cpl =
5276 : {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }};
5277 :
5278 0 : if (spdk_nvme_cpl_is_error(cpl)) {
5279 0 : NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n");
5280 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5281 0 : return;
5282 : }
5283 :
5284 0 : if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) {
5285 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset);
5286 0 : ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size;
5287 0 : ctrlr->fw_offset += ctrlr->fw_transfer_size;
5288 0 : ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size;
5289 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5290 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5291 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5292 0 : if (res) {
5293 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n");
5294 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5295 0 : return;
5296 : }
5297 :
5298 0 : if (ctrlr->fw_transfer_size < ctrlr->min_page_size) {
5299 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED;
5300 : }
5301 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) {
5302 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n");
5303 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5304 0 : fw_commit.bpid = ctrlr->bpid;
5305 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION;
5306 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5307 : nvme_write_boot_partition_cb, ctrlr);
5308 0 : if (res) {
5309 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5310 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5311 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5312 0 : return;
5313 : }
5314 :
5315 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE;
5316 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) {
5317 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n");
5318 0 : memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
5319 0 : fw_commit.bpid = ctrlr->bpid;
5320 0 : fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION;
5321 0 : res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit,
5322 : nvme_write_boot_partition_cb, ctrlr);
5323 0 : if (res) {
5324 0 : NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n");
5325 0 : NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca);
5326 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5327 0 : return;
5328 : }
5329 :
5330 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE;
5331 0 : } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) {
5332 0 : NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n");
5333 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl);
5334 : } else {
5335 0 : NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n");
5336 0 : ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl);
5337 0 : return;
5338 : }
5339 : }
5340 :
5341 : int
5342 0 : spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr,
5343 : void *payload, uint32_t size, uint32_t bpid,
5344 : spdk_nvme_cmd_cb cb_fn, void *cb_arg)
5345 : {
5346 : int res;
5347 :
5348 0 : if (ctrlr->cap.bits.bps == 0) {
5349 0 : return -ENOTSUP;
5350 : }
5351 :
5352 0 : ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING;
5353 0 : ctrlr->bpid = bpid;
5354 0 : ctrlr->bp_write_cb_fn = cb_fn;
5355 0 : ctrlr->bp_write_cb_arg = cb_arg;
5356 0 : ctrlr->fw_offset = 0;
5357 0 : ctrlr->fw_size_remaining = size;
5358 0 : ctrlr->fw_payload = payload;
5359 0 : ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size);
5360 :
5361 0 : res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset,
5362 : ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr);
5363 :
5364 0 : return res;
5365 : }
5366 :
5367 : bool
5368 43 : spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
5369 : {
5370 43 : assert(ctrlr);
5371 :
5372 43 : return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
5373 : strlen(SPDK_NVMF_DISCOVERY_NQN));
5374 : }
5375 :
5376 : bool
5377 20 : spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr)
5378 : {
5379 20 : assert(ctrlr);
5380 :
5381 20 : return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype);
5382 : }
5383 :
5384 : int
5385 0 : spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5386 : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5387 : {
5388 : struct nvme_completion_poll_status *status;
5389 : int res;
5390 :
5391 0 : status = calloc(1, sizeof(*status));
5392 0 : if (!status) {
5393 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5394 0 : return -ENOMEM;
5395 : }
5396 :
5397 0 : res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
5398 : nvme_completion_poll_cb, status);
5399 0 : if (res) {
5400 0 : free(status);
5401 0 : return res;
5402 : }
5403 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5404 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n");
5405 0 : if (!status->timed_out) {
5406 0 : free(status);
5407 : }
5408 0 : return -ENXIO;
5409 : }
5410 0 : free(status);
5411 :
5412 0 : return 0;
5413 : }
5414 :
5415 : int
5416 0 : spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
5417 : uint16_t spsp, uint8_t nssf, void *payload, size_t size)
5418 : {
5419 : struct nvme_completion_poll_status *status;
5420 : int res;
5421 :
5422 0 : status = calloc(1, sizeof(*status));
5423 0 : if (!status) {
5424 0 : NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n");
5425 0 : return -ENOMEM;
5426 : }
5427 :
5428 0 : res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
5429 : nvme_completion_poll_cb,
5430 : status);
5431 0 : if (res) {
5432 0 : free(status);
5433 0 : return res;
5434 : }
5435 0 : if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
5436 0 : NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n");
5437 0 : if (!status->timed_out) {
5438 0 : free(status);
5439 : }
5440 0 : return -ENXIO;
5441 : }
5442 :
5443 0 : free(status);
5444 :
5445 0 : return 0;
5446 : }
5447 :
5448 : uint64_t
5449 1 : spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
5450 : {
5451 1 : return ctrlr->flags;
5452 : }
5453 :
5454 : const struct spdk_nvme_transport_id *
5455 0 : spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
5456 : {
5457 0 : return &ctrlr->trid;
5458 : }
5459 :
5460 : int32_t
5461 17 : spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
5462 : {
5463 : uint32_t qid;
5464 :
5465 17 : assert(ctrlr->free_io_qids);
5466 17 : nvme_ctrlr_lock(ctrlr);
5467 17 : qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
5468 17 : if (qid > ctrlr->opts.num_io_queues) {
5469 2 : NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n");
5470 2 : nvme_ctrlr_unlock(ctrlr);
5471 2 : return -1;
5472 : }
5473 :
5474 15 : spdk_bit_array_clear(ctrlr->free_io_qids, qid);
5475 15 : nvme_ctrlr_unlock(ctrlr);
5476 15 : return qid;
5477 : }
5478 :
5479 : void
5480 64 : spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
5481 : {
5482 64 : assert(qid <= ctrlr->opts.num_io_queues);
5483 :
5484 64 : nvme_ctrlr_lock(ctrlr);
5485 :
5486 64 : if (spdk_likely(ctrlr->free_io_qids)) {
5487 64 : spdk_bit_array_set(ctrlr->free_io_qids, qid);
5488 : }
5489 :
5490 64 : nvme_ctrlr_unlock(ctrlr);
5491 64 : }
5492 :
5493 : int
5494 2 : spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr,
5495 : struct spdk_memory_domain **domains, int array_size)
5496 : {
5497 2 : return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size);
5498 : }
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