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#define | SPDK_IOAT_PCI_CHANERR_INT_OFFSET 0x180 |
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#define | SPDK_IOAT_INTRCTRL_MASTER_INT_EN 0x01 |
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#define | SPDK_IOAT_VER_3_0 0x30 |
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#define | SPDK_IOAT_VER_3_3 0x33 |
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#define | SPDK_IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 |
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#define | SPDK_IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 |
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#define | SPDK_IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 |
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#define | SPDK_IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 |
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#define | SPDK_IOAT_CHANCTRL_ERR_INT_EN 0x0010 |
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#define | SPDK_IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 |
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#define | SPDK_IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 |
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#define | SPDK_IOAT_CHANCTRL_INT_REARM 0x0001 |
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#define | SPDK_IOAT_DMACAP_PB (1 << 0) |
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#define | SPDK_IOAT_DMACAP_DCA (1 << 4) |
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#define | SPDK_IOAT_DMACAP_BFILL (1 << 6) |
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#define | SPDK_IOAT_DMACAP_XOR (1 << 8) |
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#define | SPDK_IOAT_DMACAP_PQ (1 << 9) |
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#define | SPDK_IOAT_DMACAP_DMA_DIF (1 << 10) |
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#define | SPDK_IOAT_CHANCMD_RESET 0x20 |
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#define | SPDK_IOAT_CHANCMD_SUSPEND 0x04 |
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#define | SPDK_IOAT_CHANSTS_STATUS 0x7ULL |
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#define | SPDK_IOAT_CHANSTS_ACTIVE 0x0 |
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#define | SPDK_IOAT_CHANSTS_IDLE 0x1 |
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#define | SPDK_IOAT_CHANSTS_SUSPENDED 0x2 |
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#define | SPDK_IOAT_CHANSTS_HALTED 0x3 |
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#define | SPDK_IOAT_CHANSTS_ARMED 0x4 |
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#define | SPDK_IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL |
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#define | SPDK_IOAT_CHANSTS_SOFT_ERROR 0x10ULL |
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#define | SPDK_IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) |
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#define | SPDK_IOAT_CHANCMP_ALIGN 8 /* CHANCMP address must be 64-bit aligned */ |
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#define | SPDK_IOAT_OP_COPY 0x00 |
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#define | SPDK_IOAT_OP_FILL 0x01 |
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#define | SPDK_IOAT_OP_XOR 0x87 |
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#define | SPDK_IOAT_OP_XOR_VAL 0x88 |
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#define | SPDK_IOAT_OP_PQ 0x89 |
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#define | SPDK_IOAT_OP_PQ_VAL 0x8a |
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#define | SPDK_IOAT_OP_PQ_UP 0x8b |
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I/OAT specification definitions.